Well, all physical aspects depend on the technology. This includes the elements that make up ASICs (stdcell, memories, macros, etc...). We need to re-characterize and update all libraries and models associated with those. This can mean new synthesis, new P&R rules, new macro designs, etc... This affects everything from the netlist on down, but it can even have ramifications up through the architecture, as you might need to change some functionality, re-pipeline, change your memory usage, for example. It's a lot of work.
Somehow this reminds me of an answer Dave O. gave in a conf call during the summer of 2005 re the R520 delay. Basically he said that the tools had let you guys down, and that you'd do what you could to improve the tool capabilities so that it wouldn't happen again.
Well, I suppose to some degree that was boilerplate and best intentions. Anytime there are tooth marks in your heinie you do what you can to not have that happen again, of course. Just curious tho, was there any specific toolset improvements that flowed from that experience?