Series 5, Parhelia 2...guys where are they?

[MfA]

If it has an internal cache large enough to contain the zone than it is the exact same thing ...

 

[Xmas]

You're really confusing me

It's so patently obvious to me that this paragraph describes a TBDR that I can't see how you could interpret it differently.

The 3D graphics engine divides the frame buffer into rectangular zones

So does PVR. But they call it tiles.

and then sorts the triangles into memory by zone.

So does PVR. This process is called binning. Note that the 3D graphics engine does the sorting. Not the order of polygons sent to the graphics card is adjusted.

The 3D graphics engine then completely processes the zone, writing the pixel data to memory before proceeding to the next zone.

Again, so does PVR. It completely processes a zone. This is only possible if you defer the rendering until all triangles that affect that zone are known.

By processing only a single zone of the frame buffer at a time, the use of on-chip memory (cache) is highly optimized and each pixel in each scene is drawn only once.

So does PVR. Processing one zone/tile at a time in on-chip memory, and rendering each pixel only once.

That's genuine TBDR.

 

[Dave Baumann]

...without PowerVR's sorting...

 

[Xmas]

Which sorting do you mean?

btw, Dave, please do something about this page counting bug. It's really getting annoying

 

[Dave Baumann]

Oops, sorry, sorting is binning in PowerVR terms. The step thats missing in the Intel solution is the HSR algorithm:

http://www.beyond3d.com/articles/tilebasedrendering/index2.php

There's not a lot you can do about the threads really. The post headers and post texts are in different parts of the DB, and when there is a net slowdown sometimes one reaches the submit point of the database and the other doesn't.

 

[3dcgi]

Even if they don't perform any hidden surface removal on the post sorted/binned primitives I agree with Xmas and call it a "tiler".

 

[Dave Baumann]

Oh, I wasn't disagreeing with that myself; however "tilers" are often associated with the PowerVR method of rendering and the fact that it appears to miss one of the crucial steps can lead to some confusion. AFAIK P9's tiling works in the same fashion to Intel's.

 

[Kristof]

There is a difference between a TBR and TBDR...

 

[Xmas]

Oops, sorry, sorting is binning in PowerVR terms. The step thats missing in the Intel solution is the HSR algorithm:

http://www.beyond3d.com/articles/tilebasedrendering/index2.php

It does have the binning step ("sorts the triangles into memory by zone"), but the description from Intel doesn't explicitly mention any HSR algorithm, right. However, if they have all that data available, I find it hard to believe they wouldn't do at least something like filling the depth buffer first, or some trivial rejection of triangles.

 

[Ailuros]

There is a difference between a TBR and TBDR...

Apparently the last two pages are about wheter it defers or not the rendering. Haven't seen anything in terms of tests on the 3rd generation of Intel's "Extreme" chipsets, but if it has any relevance to it's predecessors I'd gladly categorize it under "Tilers that suck". There I said it ....oooops