Here is more information on the Saarland DRPU (Dynamic Ray Processing
Unit).
http://graphics.cs.uni-sb.de/Publications/svenwoop-drpu-thesis-V1.1.pdf
Unit).
http://graphics.cs.uni-sb.de/Publications/svenwoop-drpu-thesis-V1.1.pdf
A working FPGA prototype implementation specified in the developed
hardware description language HWML is presented, which achieves
performance levels comparable to commodity CPUs even though clocked at
a 50 times lower frequency of 66 MHz. The prototype is mapped to a 130nm
CMOS ASIC process that allows precise post layout performance estimates.
These results are then extrapolated to a 90nm version with similar hardware
complexity to current GPUs. It shows that with a similar amount of hardware
resources frame-rates of 80 to 280 frames per second would be possible
even with complex shading at 1024x768 resolution. This would form a good
basis for game play and other real-time applications.
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