If true that's not a great way to approach it, it'd be better to simply cap the maximum sum of clock speeds of the two clusters at the kernel level or something (nVidia for example has done things like this) Fixing different maximum clock speeds to the two clusters is going to force more migrations than necessary. And removes the opportunity of running the cores at full clock speed in the most permissive thermal environments.
I suppose the possibility exists that they simply can't, especially if this decision wasn't settled until late in development. Actually having the L3 physically there would make the scenario of a late kludge more likely.
Maybe their DVFS isn't smart enough, or could not be validated/bug-fixed well enough for a fully dynamic setup.
Having an L3 and not being able to use it has certain other possibilities, such as some kind of synchronization issue or consistency problem akin to AMD's TLB issue.
At any rate, I am curious about how the Anandtech latency numbers are derived. Perhaps it is an artifact of mobile memory standards, but the wall-clock times are bad. Qualcomm without an (active) L3 is significantly worse than Apple's A9 with an L3, which is worse than the A9X by an amount that seems consistent with the latency of an exclusive L3 access.
The derived values for the AMD-powered consoles are very poor, but still better than the mobile ARM chips. AMD's higher-power APUs are bad but faster than the consoles, and then there's AMD's non-APU CPUs that were decent, then pretty much any modern Intel design at the forefront.
Indeed, they'd better hope that the cluster they're binning for smaller L2 cache because of defects also happens to be the cluster that they're binning for lower clock speed.
I've given this some additional thought, and I think that slashing half the L2 and dropping the max clock somewhere below the inflection point for the power curve provides a lot of wiggle room, perhaps more than needing to worry about intra-cluster variation except maybe as a secondary consideration. If for some reason the chip's power is that borderline where one cluster has defects and the other runs hot, it might be in the corner case that Qualcomm would decide to discard.