Qualcomm SoC & ARMv8 custom core discussions

Poor on its own:

http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/11

Turns out that ended up being the best implementation on 20nm! It seems that licensees did not need more experience with the ip, just a new node.

 

This still doesn't really mean anything without context. I'm going to take it that what you mean here is that both TSMC and Samsung's 20nm were actually less efficient than their 28nm node. But how would you determine that from the AT article? Are you comparing it to a Cortex-A57 same revision implementation on 28nm? Because it looks like you're comparing a particular revision of A15 to particular revision A57, which is not really fair to isolate process differences.

If you instead compare the Cortex-A15 in Exynos 5420 (Samsung 28nm) with that in Exynos 5430 (Samsung 20nm) you get this: http://www.anandtech.com/show/8718/the-samsung-galaxy-note-4-exynos-review/2 Kind of paints a different picture than "poor process"

 

ARM described several power improvements in AFAIK r4 of Cortex-A15. nVidia cited these changes as a contributing factor to higher efficiency in Tegra-K1 over Tegra 4. It's not clear to me if all of these modifications even made it into A57, or at least initial revisions.

The line between mere revisions and new core names can be fuzzy. In a lot of ways Cortex-A72 looks like a couple major revisions ahead of A57. and I think we can all agree the power consumption improvements appear substantial. A17 also appears to have started out as some revisions to A12.

Which looks very, very bad for Qualcomm's implementation of A53, which by all means should be an intrinsically more efficient processor than Krait 400. Which again leads me to wonder how good of a job they even did on their 28nm A53 implementations. I don't think I've seen measurements here. What I do know is that the Xperia M4 Aqua phone with S615 has very, very messed up scheduling that makes me wonder if they're trying to haphazardly cover for poor efficiency.

Any chance we'll see something like this performed on a Jetson X1 board? Should be pretty easy. Maybe AT could get a review sample if you didn't already.

 

What do you mean by context? The phone routinely needs to throttle due to its power consumption. The 5433 (the ~best 20nm implementation of A57) can consume over 7w at max load! That's just bad in general (especially for phones where throttling will happen in seconds). No comparisons to other SoCs are needed.

Remember the original question:

Sure you can blame qualcomm for making the situation worse, but the reality is even if qualcomm matched the best 20nm implementation of the A57, it still would have appeared "bad" compared to the 7420. Look at that graph Neb provided us, I'd say the 5433 is also "bad" compared to the 7420 (the gap between the 7420 and the 5433 is larger than the gap between the 5433 and 810).

Ultimately I can't blame TSMC's implementation of 20nm or qualcomm for the 810's failures. Qualcomm was never going to look good (in this market) until its SoCs moved to finfet (or perhaps a custom core). Sure they could have done better with the A57, but would have it really mattered? Was it ever going to be competitive against the 7420?

 

I doubt the A57 implementation or the process is to blame for S810 mischiefs; the majority of so far indications point at a problematic memory controller.

 

So none of that means that Samsung's 20nm is a "poor process." I can find 28nm phones that can use 7W at full load too. Pretty much no phone with a processor like Cortex-A15 or A57 is allowed to run all cores at max clock speed indefinitely, including on Samsung's 14nm. Of course comparisons to other SoCs are needed, you can make an SoC that uses 7+W on any process.

The point is, you're just not isolating every variable. I showed that Exynos 5430 is a lot more power efficient than 5420 but this doesn't seem to matter to you. By your reasoning, 5430, 5433, and Tegra X1 shouldn't have been made at all, they should have just been skipped for 14/16nm SoCs right? But you can't survive at all in this market by not releasing a product. Despite having terrible efficiency Qualcomm's 808 and 810 SoCs still got many design wins, I think it's obvious that they would have been in a poorer position had they opted to sit out and wait for 16nm. But of course them doing a better job would have mattered, it would have made their PR not nearly as bad and it would have gotten them a few more wins. This isn't an all or nothing game where they're either the best Android SoC or nothing matters given that not everyone buys Samsung devices and their high end SoCs have been mostly limited to said devices.

 

Really? I stand corrected. Then why is the GPU throttling like no tomorrow? Adreno330 didn't throttle by such an absurd persentage.

 

http://images.anandtech.com/doci/8718/big-cluster.png
Look at the difference: 2 A57s at max clock/load consume about the same power as 4 A15s!

I didn't say samsung had a poor process. I'm saying the A57 (regardless who did the implementation) was underwhelming for a phone SoC on both samsung's and tmsc's 20nm processes.

Yes you showed me how a 28nm SoC (5420) became more power efficient on 20nm (5430). I'll give you 20nm wasn't very good for power, but that's hardly a valid comparison for this situation. But regardless, what kind of efficiency gains were you expecting? Even if they developed a SoC 50% more power efficient than the 5433, it would still be behind the 7420. I'd be surprised if they could achieve those gains in that time frame.

As to what they should have done, that's orthogonal to the question. I didn't say they made the wrong decision or that they should have waited for finfet. I'm only suggesting that in general we shouldn't expect a 20nm A57 SoC to be competitive to a 14nm (finfet) A57 SoC and that imo the A57 turned out to be pretty mediocre on 20nm.

 

The 808 and 810 A53 curves get closer in the performance range where one would expect active power to dominate. Perhaps less than perfect idling or gating on the 810 leaves a higher power floor?

 

I am trying to draw inferences from what was given in the graph, and this seemed somewhat ambiguous.
Without knowing what exactly goes into the W component, it didn't look inconsistent with having to deal with a component of non-dynamic power consumption that becomes less dominant as the chip starts to go higher in the design's clock range.
The behavior of the Exynos A53s at 16nm and 20nm Samsung, with the significantly higher perf/W at the lower range seems consistent with the more significant scaling of static and sub-threshold consumption by FinFET versus planar.

The picture didn't indicate either way on whether the measurements excluded SOC power consumption besides the A53s. (edit: and active-only on top of that)
As far as judging the quality of Qualcomm's implementation how many examples for each SOC go into the curves?

I'm curious if there's anything you've seen that illuminates why Samsung's curves have a gap in absolute performance between the A53 and A57 cores, whereas Qualcomm allows more overlap at the apparent price of including that less-than ideal part of the OoO cores' curve.

 

Out of curiosity, does the 808's A53 curve end sooner on the X axis than the corresponding cluster on the 810?
Is using performance as the X axis enough of a proxy for the clock/voltage points being used?
It might be coincidental, but it would be an interesting correlation if the dynamic range on one side has implications for the other. Both clusters for Qualcomm seem to follow a similar philosophy of a more full curve from the 801, rather than the more truncated range done by Samsung.

 

I think there should be at least some familial resemblance in cluster behavior for SOCs of the same generation from the same designer.
The 808 and 810 A57 lines have a gap in max performance as well, but there could be various reasons for why one has a greater range in achievable performance than the other.

That one has a reason to have so much overlap or lacks of everyone else's reasons for a gap seems interesting to me.

I just wanted to confirm that the SPEC score at point X sufficiently close to where the core's clock is set relative to its min and max.
Performance is a value that results from the contribution of multiple factors, and the reasons for changes in slope or a difference in where a curve ends on the X axis could vary.
I am curious where the cores are in their frequency range, whereas performance achieved is at least partly an architectural/software phenomenon.