PS3's CPU, GPU, RAM and eDRAM configuration?

[London Geezer]

That would be 368GB/s at 4GHz, unless i got it wrong

bus speed is half, 2 ghz

Oh ok, then it's a bit less than 200GBs.

 

[j^aws]

Could the GPU use a EIB? Is the EIB a Rambus tech?

 

[version]

Could the GPU use a EIB? Is the EIB a Rambus tech?

not rambus, eib is a ring
and yes gpu do it

 

[j^aws]

Could the GPU use a EIB? Is the EIB a Rambus tech?

not rambus, eib is a ring
and yes gpu do it

Yes, it's a ring bus...but who's technology is it, IBM's? ...IIRC, there was an IBM ring bus patent...but I don't know if it's related...is it a IBM's or Rambus design?

 

[version]

Jaws,you read sony gpu patent? what you mean real time raytracing ?

 

[London Geezer]

Jaws,you read sony gpu patent? what you mean real time raytracing ?

Oh not again!
What part of not gonna happen do u not understand?
Really, realtime raytracing is both extremely performance sucking and in the end, not really necessary. Maybe used for shadows, but that's a very small part of the potential engine. Raytraced reflections and refractions are impossibly inefficient and will not run well even on the next gen architectures (unless a miracle happens of course).

 

[j^aws]

Jaws,you read sony gpu patent? what you mean real time raytracing ?

Shhhhh....

Btw, which Sony GPU patent are you referring to?

I'm still trying to find that ring bus patent...

 

[version]

in sony's patent a trick with fast cubemappig for RT

 

[j^aws]

in sony's patent a trick with fast cubemappig for RT

Nope...not read that, a link please?

 

[London Geezer]

in sony's patent a trick with fast cubemappig for RT

Yeah, fast cubemapping to fake RT. Not realtime RT.

But hey, if some parts of the graphics engines will feature some form of RayTracing i'll be more than happy. We already kinda do anyway.

 

[j^aws]

This is a ring bus patent by IBM, nAo, should be familiar with it.

Ring-topology based multiprocessor data access bus...

I have to read it again to see if it's the EIB...

 

[version]

in sony's patent a trick with fast cubemappig for RT

Nope...not read that, a link please?

http://appft1.uspto.gov/netacgi/nph...0066384&OS=20040066384&RS=20040066384

 

[j^aws]

Ta... I've posted the ring bus patent above... ^^^

 

[j^aws]

in sony's patent a trick with fast cubemappig for RT

Nope...not read that, a link please?

http://appft1.uspto.gov/netacgi/nph...0066384&OS=20040066384&RS=20040066384

Ahh that patent! ...Yes I've read it, but IIRC, the RT was for HSR, and nothing mentioned for secondary rays?

 

[version]

Furthermore, it is known that Sony originally said it would reveal more details on the PlayStation 3 at a premiere event in Japan on March 31, 2005

http://www.xbitlabs.com/news/multimedia/display/20050211020425.html

yes

 

[j^aws]

what you mean this?

If you replace 'Control' in GPU with a PPE then you basically have two CELL processors (except for the RPE)

Btw, the ring bus patent sounds pretty much like the EIB but they describe a 576 bit bus instead...

 

[version]

hmm 576 bit bus fast , possible some SPE in gpu with 64 bit ring and 512 bit for renderprocessors

 

[Shinjisan]

Just a question for you tech experts.

Each Cell has two XDR channel which support up to 4 DRAM chips.
Is it possibile to have just two DRAM chips,one for channel?

 

[Acert93]

Total guess...

F.

CPU => 256MB
GPU => ~40MB eDRAM

1 CELL (1 : 8) and 1 GPU (~600MHz, 16x1 or 16x2; I would be shocked at something over 32 unless there is no eDRAM). CELL SPEs do vertex shading (although I would think the GPU would be more effecient at this per-transistor) and GPU will be able to read from CPU cache. GPU will mainly focus mainly on pixel related functions. Possibly a slower 2ndary pool for RAM (similar to GCN).

Again just a guess (not what I want... that would be 512MB of shared XDR, 2 CELLS or even 4 1:4 CELLS, and a massive GPU... a BR cherry on top).

It would be interesting to start a thread where everyone posted what they think the final specs of each system will be (Xenon and PS3) and the thread starter copy/paste them into the first post. And when the new systems come out we can see who was actually the closest. That also prevents people from saying, "I was dead on" when in fact they made 10 guesses and a lot of stuff never made it.

 

[j^aws]

Just a question for you tech experts.

Each Cell has two XDR channel which support up to 4 DRAM chips.
Is it possibile to have just two DRAM chips,one for channel?

Sorry, I don't really understand the question...

XIO memory controller = 2 XDR interfaces

XDR interface = 2 Channels

1 Channel = 16 bit

Therefore XIO controller = 4 channels * 16 bit = 4 * XDR RAM chips @ 64 bit bus

I suppose they can vary these...but this is what Rambus state IIRC...