"PS3 Reference Tool" Ram Type Overlooked?

There are a couple theories to this...

Assuming that the 4 memory module (unsure if they are single or dual banked) per Cell CPU is still hardware limited (they can redesign the memory controller in the future to support more memory modules), either they are accounting for the fact that they expect to have 1024Mbit XDRAM (128MByte) modules ready for those final PS3 devkits *OR* they plan on putting TWO Cell CPUs in those final PS3 devkits using the current 512Mbit XDRAM (64MByte) modules.

It would not surprise me either way... and as people have already said devkits typically do have more memory than the consumer version.
 
Reading the link posted it's obvious that Cell can support more than 4 memory modules, but is limited to a 36bit bus. Normally XDR modules have a 16bit bus, so each memory channel in Cell supports 2 modules. If you want to support a total of 8 modules each one now has the equivalent of an 8bit bus. Memory capacity went up, but bandwidth did not.
 
Thowllly said:
The way XDR works, I don't see how it would be possible for it to be hardwired for any number of chips. XDR has one address bus that is output only, and all addresses goes to all the chips. The address bus works at 1/4 the speed (in transfers/s) of the data bus and is basically the same as the bus that's used RDram (for both data and address) except that it's only used as an output bus for addresses. The data bus is 36 bits wide (32 data + 4 ECC) and used for both input and output. Each of these data lines is connected to one chip and one chip only. There can be any number of chips as long as all 36 data lines (or 32 without ECC) are connected to one chip and one chip only. So you could use 7 chips that are 3 bits wide, plus one chip that's 11 bits wide for a total of 32. The only reason I can think of for the low amount of memory is because for now there only exists XDR chips that are 16 bits wide with 32M words, or something like that.

XDR looks very flexible in the digital domain, but at the speeds it operates, analog parasitics become major engineering obstacles, so it's not entirely obvious, at least to me, that what's theoretically possible is realizable in hardware in short order.

Samsung makes 512Mb XDIMMs in 256Mx2, 128Mx4, 64Mx8, and 32Mx16 organizations, so the chips are available for hooking up more than 4 to the Cell.

Anyway, even the author of the Real World Tech article people are citing to "prove" that Cell can support >4 XDR devices offers the following caveat:

David T. Wang said:
In order to support the XDR DRAM device in such a configuration, specific support must be built into the XDR DRAM controller interface. To date, IBM has not released details on the memory controller interface indicating whether the current incarnation of the CELL processor can support a 72 DRAM device configuration in the XDR memory system, or a less amount, i.e. 36 DRAM devices.
 
OtakingGX said:
Reading the link posted it's obvious that Cell can support more than 4 memory modules, but is limited to a 36bit bus. Normally XDR modules have a 16bit bus, so each memory channel in Cell supports 2 modules. If you want to support a total of 8 modules each one now has the equivalent of an 8bit bus. Memory capacity went up, but bandwidth did not.


Well that's all that really matters though when you're problem is simply memory capacity. For the pinout in the first place, its definitely some quality bandwidth you're getting, even if you're limited in the sense that adding memory modules will not increase bandwidth under normal (single Cell) circumstances.
 
hugo said:
With the introduction of GDDR4 and the reduction of the XDR cost you can't rule out the possibility of it.Sony may up their XDR size in the PS3 at the last minute if they wanted to.

Sure then could, hell at this point they could stick more cells in there...... BUT

It's all about cost over time, and the reason MS hovered at 256Mb's for so long was because one of the things that hurt them in Xbox later in life was the larger RAM. RAM just doesn't come down in cost at the same rate as logic heavy chips.

At this point I'd be surprised if there were any significant spec change.
 
phat said:
XDR looks very flexible in the digital domain, but at the speeds it operates, analog parasitics become major engineering obstacles, so it's not entirely obvious, at least to me, that what's theoretically possible is realizable in hardware in short order.
For the data bus, every data line is connected to only one memory chip no matter what the configuration is, so the number of memory chips does not affect it. The address bus is an rdram bus running at only 800Mt/s, it's an old bus standard that has been used on many old motherboards that support at least 2 modules with at least 8 chips each, at higher speeds than 800Mt/s. Also, with XDR ram the bus is only used as an unidirectional bus. I cannot think of a reason why the cell would be any less capable than those old chipsets used on those MBs.

Anyway, even the author of the Real World Tech article people are citing to "prove" that Cell can support >4 XDR devices offers the following caveat:
Well, I haven't cited him, his article has nothing to do with what I believe. I simply can not see any logical reason why the cell would be limited to 4 memory chips, for the reasons I mentioned above.
 
Ram is most likely going to be the most expensive or at least one of the most expensive things in the next gen system and so i don't see sony suddenly adding another 50% cost to the ram .

Esp not the more expensive ram that is only being produced for the ps3 and some cell servers . If they add any ram imho it be gddr ram as that is mass produced and used in graphics cards and will quickly become cheaper as its moved down the speed ramp
 
The GameMaster said:
Assuming that the 4 memory module (unsure if they are single or dual banked) per Cell CPU is still hardware limited
You've already been informed there exists no such limit in Cell; read the thread. The 4-chip limit was an imagined one based on faulty assumptions. Besides, XDR doesn't use banks in the sense DIMMs do, it's a serial, packetized system outside of the silicon DRAM arrays themselves.
 
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