Shifty Geezer said:Which makes sense. Basically there is no official Cell<<GDDR memory BW, no Cell<<GDDR lines, and that 16 MB/s is jumping through hoops to access the GDDR which accounts for it being so slow, presumably making requests of the RSX to fetch and deliver. For clarity I'd like to see a table of dependences or how these BWs interact, showing how one data path affects another data path reducing available BW. eg. Using 22.4 GB/s RSX<<GDDR means 0 GB/s RSX>>GDDR. Does that 16 MB/s Cell<<GDDR consume some or all of that BW, or the 4 GB/s read BW, or 16 MB/s of the RSX>>Cell BW, or what?
The 16MB/s figure has got to be wrong. It is impossible to make a modern inter-processor bus interface go that slow without artificially limiting it. To put it into context, the 16MB/s data transfer rate is half the speed of a UDMA 33 IDE hard drive. Either the 16 MB/s is a typo and should read 16 GB/s, or it has to be some sort of built-in automatic DMA transfer designed to keep the RSX fed with commands or something without GDDR bus contention.
The link http://portable.joystiq.com/2006/06/05/rumor-ps3-hardware-slow-and-broken/ does seem to show that RSX can read and write to XDR at 20GB/s and 15GB/s respectively (if there is anything credible about the link). However Mercury's datasheet for a 2 CPU Cell blade communicating over the Flex i/o lists it as an SMP system with full cache and memory coherence rather than an NUMA system http://www.mc.com/literature/literature_files/Cell_blade-ds.pdf . Therefore the secomd CPU must be able to access the first's XDR memory over the Flex i/o interface as fast as it can access it's own, which seems to lay to rest the idea that the XDR cannot be accessed via Cell without excessive latency.
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