PS3 devkit
- Thread starter one
- Start date
And your point being ........ All your doing is furthering my arguement .
The spes have small local storage , i highly doubt this will be enough for anything sony talked about in thier videos . They are going to have to hit main memory . quoting those band width numbers is about as wrong as adding the 256gb bandwidth of the edram to logic .
No it's not. If I am unpacking compressed data in an SPE, at say 10:1, I only need 10% of XDR bandwith to saturate the pipe to RSX.
Or how about if I decided to tile my framebuffer into size that fits SPE localmemory, and do all my back-buffer rendering inside a localstore. Most of the FlexIO bandwith would again not be used to access XDR.
And that's just tip of the iceberg really.
Or, a fully controlled cache, if a programmer programs it so. It can be programmed not to hit the main memory too. Anyway, you have EIB in Cell so I guess it's an overhead too.PC-Engine said:
Eh, with what are you comparing it?jvd said:
PS3 dev kit = 256bit bw to VRAM (38.4GB/s) + PCI-E 4x from main memory (2GB/s) - X (Cell access overhead)
PS3 = 128bit bw to VRAM (22.4GB/s) + FlexIO from main memory (20GB/s) - X (Cell access overhead)
I don't think X is very different between these 2.
EDIT: Also, a devkit has a 2.4Ghz Cell, so the memory clock would be lower.
Avon_Implosion
Newcomer
teamxbox just got word of the dev kits,
http://news.teamxbox.com/xbox/8565/PlayStation-3-SDK-Revealed-First-Pictures-Spotted/
however, what i find interesting is they're claiming that the RSX was running and fully functional in those dev kits
http://news.teamxbox.com/xbox/8565/PlayStation-3-SDK-Revealed-First-Pictures-Spotted/
however, what i find interesting is they're claiming that the RSX was running and fully functional in those dev kits
jvd : What's wrong with quoting the system peak design metrics? How else do you describe the avaiable BW to RSX or any other component? 56 GB/s to RSX total is availible. You're right that the RSX won't ever see that much, but it is there. It's the same as saying Xenos has 22 GB/s BW to RAM, which doesn't factor in that that is shared with XeCPU.
Peak metrics aren't performance indicators as we all know, but they're the only way to accurately decribe a system, as no-one can say how much BW one component will be using vs. another. How much will Cell be gobbling up of that 56 GB/s figure? Depends on the software. As such no figure can be placed on available bandwidth, only total BW, the same as any hardware, and leave it open to devs what they want to do with that.
Peak metrics aren't performance indicators as we all know, but they're the only way to accurately decribe a system, as no-one can say how much BW one component will be using vs. another. How much will Cell be gobbling up of that 56 GB/s figure? Depends on the software. As such no figure can be placed on available bandwidth, only total BW, the same as any hardware, and leave it open to devs what they want to do with that.
Never trust my quotes on actual figures - I can never remember details!
But the point about the 256 GB/s figure is different. MS were claiming this was 1) a bandwidth figure eslewhere in the system (into the eDRAM, not internal to the eDRAM) and 2) they included that figure in system aggregate BW without fairly including other internal bandwidths for XB360 or PS3. It's the misrepresentation of the figure that makes it unfair in most occassions it's used.
A claim of 256 GB/s BW inside the chip is fair and accurate and I have no complaint with it. Just as I have no complaint with 22 GB/s Xenos to RAM AND 22 GB/s XeCPU to RAM, despite that figure being a shared bus. Just as I have no complaint with 48 GB/s BW available for Cell and RSX. These are accurately portrayed peak specs and represent the absolute limits available to differen system components. Now if nVidia/Sony were to start saying RSX has 700 GB/s BW because it can write directly to Cell SPE's LS, then I'll get huffy
But the point about the 256 GB/s figure is different. MS were claiming this was 1) a bandwidth figure eslewhere in the system (into the eDRAM, not internal to the eDRAM) and 2) they included that figure in system aggregate BW without fairly including other internal bandwidths for XB360 or PS3. It's the misrepresentation of the figure that makes it unfair in most occassions it's used.
A claim of 256 GB/s BW inside the chip is fair and accurate and I have no complaint with it. Just as I have no complaint with 22 GB/s Xenos to RAM AND 22 GB/s XeCPU to RAM, despite that figure being a shared bus. Just as I have no complaint with 48 GB/s BW available for Cell and RSX. These are accurately portrayed peak specs and represent the absolute limits available to differen system components. Now if nVidia/Sony were to start saying RSX has 700 GB/s BW because it can write directly to Cell SPE's LS, then I'll get huffy
I know. I was stating that example as a phoney representation of specs. Just because SPE's might have 700 GB/s (or whatever the figure is) internal bus, doesn't make it a fair claim that RSX can communicate with Cell at that speed - analogous to claims Xenos parent die can talk to daughter die at 256 GB/s.
