upnorthsox
Veteran
Does anyone have (roughly) accurate figures on what the transistor count is per MB of IBM eDRAM tech? Power7 is a 567mm2 design at 45nm with 1.2bn transistors. Some die shots here:
http://aceshardware.freeforums.org/power-7-t891-15.html
Seems to be packed quite dense. Fitting ~20MB in a 2bn transistor 22nm console integrated CPU/GPU shouldn't be too difficult assuming it scales near linearly (I'm guessing it won't?). Looks like too big a design win to pass up, but I'd like some accurate figures to work with.
20MB would be enough to fit an entire 1080p framebuffer (assuming no msaa since MLAA and its derivatives will probably be much more popular next generation) and still have a decent amount of space left over to work as a generic CPU L3 cache as well. With MRTs becoming so popular it seems silly to go with much more than that as no amount of L3 cache is ever going to be big enough to fit all your render targets at once, so long as they can each easily be swapped in and out of cache then I think the solution is fine.
Not sure of the die size but its 2bn transistors for 32MB of edram at 45nm. Looking at the die I'd say it's at most 1/3 and probably less of the 567mm2. That'd put it at 189mm2 at 45nm or about 59mm2 at 28nm for 20MB with 1.2bn transistors.