IBM's POWER5 design is rather like the POWER4 design, being dual-core with some L2 cache on-die and a large external L3 cache, in a Multi-Chip Module (MCM). POWER5 systems to replace the current POWER4+ based systems are expected to launch by the end of 2004, 3 years after the original POWER4. All parts of the design have been enhanced to increase performance, while also trying to keep power consumption reasonable. Today, IBM's largest POWER4 servers can take 16 POWER4 processors (32 cores), and for the next generation, IBM are working on a system code-named Squadron that will take 32 POWER5 processors (64 cores, and 128 hardware threads).
The POWER5 will be 389mm² on IBM's 130nm SOI process, run at up to 2GHz and contains 276 million transistors. On the same process, the POWER4+ is 267mm². Though the basic pipeline is the same as the POWER4, the amount of resources has been increased to better optimise for the 2-thread SMT capable cores, which increases the core sizes by about 24%. These resource increases include rename registers, instruction-fetch buffers, and the whole cache design. The SMT threads can also be assigned different priorities, so better optimise the resource allocation - for example, lower the priority of a thread waiting on a lock or I/O. In server tasks, SMT is expected to improve overall performance by around 40% (will vary from benchmark to benchmark of course).
