PowerVR Series 7

Discussion in 'Mobile Graphics Architectures and IP' started by roninja, Jun 29, 2014.

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  1. Ryan Smith

    Ryan Smith Regular

    Odd. Your Series6XT press release says otherwise.

    http://www.imgtec.com/news/detail.asp?ID=821

     
  2. alexvoica

    alexvoica Newcomer

    Series6, Series6XT and Series7XT GPUs are all based on the Rogue architecture. Series6 and Series6XT go up to 10, while Series7XT can handle 11 with the feature pack. Sounds okay to me?
     
  3. http://blog.imgtec.com/powervr/powervr-g6630-go-fast-or-go-home

    It's more the earlier Series6 releases where it reads like certain Series6 family members support DX11 rather than some members of the Rogue architecture in general support DX11. But I guess the separation between Series6 and Series7 might not even have been fully defined back then.
     
  4. Ailuros

    Ailuros Epsilon plus three Legend Subscriber

    Splitting up "Rogue" as an architecture into more than one generations is clearly a marketing decision. I wouldn't be at all surprised if it reaches to Series8 also. If you add things up the difference between Series6 and Series7XT cores can go up to >+100%. Either perspective you take there seems to be a LOT of headroom to scale performance for Rogue. What marketing then decides to call each is another story. If you backflash and compare a SGX530@250MHz and a SGX554MP4@250MHz you get a difference of 32x times in GFLOPs as one singled out value.

    By the way I assume from Ryan's text:

    http://www.anandtech.com/show/8706/imagination-announces-powervr-series7-gpus-series7xt-series7xe

    ....that if FP64 is requested, it gets added as dedicated FP64 units and it's not that existing ALUs get used for 1:2. If you'd tell me it's the latter it would build quite a design philosophy oxymoron in my mind compared to the FP32/FP16 ALUs story.
     
    Last edited: Nov 11, 2014
  5. Lazy8s

    Lazy8s Veteran

    The Anandtech article added some nice tidbits on the implementation, relevance, and reasoning for inclusion of Series7's new features. I'm glad it got coverage.

    The priority on improving efficiency while adding some additional scalability has the potential to make Series7 a solid update.
     
  6. Ailuros

    Ailuros Epsilon plus three Legend Subscriber

  7. Ailuros

    Ailuros Epsilon plus three Legend Subscriber

  8. Arun

    Arun Unknown. Legend

    ok!
     
  9. sebbbi

    sebbbi Veteran

  10. Exophase

    Exophase Veteran

    So back to the integer SIMD capabilities of Series 5?
     
  11. Arun

    Arun Unknown. Legend

    IIRC SGX didn't support Vec2 INT16, only Vec2 FP16 and Vec4 INT8. Either way it's a new pipeline :)

    There are a few things slightly wrong in the article but I'm not sure what I can say publicly. One thing I can definitely say because it's obvious from the diagram: the "Image Processing Data Master" uses the USC and texture units for processing. This means it's actually *less* fixed-function than the original Series6 which had a dedicated 2D accelerator. It is lower area and its performance scales 'for free' with the number of USCs, while being more efficient than using the pixel data master *and* being able to run in parallel to an unrelated 3D task.

    So 7XTP can run multiple programs of 4 different kinds (vertex, pixel, compute, image) at the same time on the same USC.
     
  12. Ailuros

    Ailuros Epsilon plus three Legend Subscriber

    Arun & sebbi,

    Nothing against that at all, au contraire. I was (and am probably not the only one....) expecting a few details about Series8 mostly. Unless of course marketing has changed its mind and skipped the per year "generation" numbeing scheme after all.

    Anyway I know it's probably hard if not impossible but on average how much more efficient could one rate a 7400+ compared to a 7400 f.e. and why have there been released only two IP variants of it?
     
  13. Rys

    Rys Graphics @ AMD Moderator Veteran Alpha

    The number of variants announced is just marketing. As for the efficiency, Plus is mostly about in-system performance and interacting better with what you can crudely class as higher bandwidth, higher latency memory subsystems.
     
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