Backwards compatibility unofficially confirmed for PS5?
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Inventors: Cerny; Mark Evan (Burbank, CA), Simpson; David (Los Angeles, CA)
Filed: January 20, 2017
Cerny , et al. October 16, 2018
Simulating legacy bus behavior for backwards compatibility
Abstract
To address problems that arise due to differences in bus behavior when running a legacy application on a new device the new device may throttle bus performance in a way that emulates the bus behavior of a legacy device when executing the legacy application.
Bus throttling on the new system may be based on estimated bandwidth allocations determined from behavior of the legacy bus. Bus traffic may be throttled by limiting the amount of available bus bandwidth allocated for particular bus transactions according to amounts estimated from the legacy bus behavior. The bus traffic is throttled so that the new device allocates at least as much bandwidth as would have been allocated by the legacy system, but not so much more that synchronization errors arise in execution of a legacy application. The throttling can be tuned while running legacy applications on the new device to determine how much additional bandwidth allocation causes problems with execution.
FIG. 1 shows an example a new device configured to account for differences in bus architecture between a legacy device and the new device when running applications written for the legacy device. In this example, the new device may include a multicore CPU and a multicore GPU coupled to a common memory 106 and I/O access controller 108. Each CPU or GPU core is coupled to a level 2 cache 110 and bus interface unit 112 via backside buses (BSB.sub.1, BSB.sub.2). The level 2 cache 110 is coupled to the memory 106 and I/O access controller 108 by a frontside bus (FSB). Additional memory (not shown), peripheral devices 114, video 116, and data storage devices 118 interface with the CPU and GPU through the access controller by various busses. The CPU and GPU may include configurable registers 105 for temporary storage of data and/or instructions. A legacy version of the device in FIG. 1 might have a different architecture, e.g., one in which there are separate busses for the CPU and GPU and in which there are separate controllers for memory and I/O access.