I thought this was a feature that Sony talked about: shortcuts that launched you into a specific part of a game, skipping intro movies and the game menu.
Yup, from the Wired interview:
Playstation 5 [PS5] [Release November 12 2020]
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Yup, from the Wired interview:
None. Whether you need 80 MB or 2 GB, you want to maximize the bus to mimimize the time that the SDD needs to access RAM.
Isn’t there just one pool of RAM?
D
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Yes, and there is no suggest that it's dual-ported. Although given Sony designed so much of the controller, that's not out of the question but you would have expected Mark Cerny to have mentioned if that was the case. Given their coherency scrubbers, dual-ported access would have made a lot of sense - at a cost.
I am thinking about this and what it really means in addition to traditional data flow if any
https://nerd4.life/2020/05/21/ps5-e...nsfer-files-from-the-ssd-directly-to-the-gpu/
https://nerd4.life/2020/05/21/ps5-e...nsfer-files-from-the-ssd-directly-to-the-gpu/
That has to do with reducing the overhead normally associated with accessing storage like an HD or a SSD. That does help with latency and speed but not bandwidth specifically. It does help a little since the faster you can get your use out of the bus the faster something else get it.
edited for minor embarrassments.
anexanhume
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Most interesting patent I’ve seen out of Sony in a while.
SCALABLE GAME CONSOLE CPU/GPU DESIGN FOR HOME CONSOLE AND CLOUD GAMING
http://www.freepatentsonline.com/y2020/0242723.html
SCALABLE GAME CONSOLE CPU/GPU DESIGN FOR HOME CONSOLE AND CLOUD GAMING
http://www.freepatentsonline.com/y2020/0242723.html
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D
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Sounds like the depiction of two SoCs doing alternate frame rendering (AFR) or split frame rendering (SFR).
AFR could probably suck less if both SoCs have access to the same memory pool, though two SoCs on the same memory pool would need to dramatically increase overall bandwidth.
Regardless, the idea of a 2xSoC PS5 Pro is really interesting. The patent itself mentioning the economics of big monolithic dies goes in line with AMD's current approach for CPUs and could indicate why Sony chose to go with a narrow GPU this time.
But looking at the alternatives it seems there's a chance that each SoC could have its own memory pool. On a 2x PS5 SoCs that would mean.. 32GB of GDDR6? Or maybe the slave SoC could disable some memory channels assuming they're not running an O.S.
I'd guess this is not an alternative for the current 7nm PS5 SoC considering how big the console is, but I could see a PS5 2023 lineup with a single-SoC PS5 plus a dual-SoC PS5 Pro, both using the same SoC made on 3nm (or a half-node post-5nm?).
Of course, they'd probably also need to implement a very wide and very fast IF bus for inter-SoC communication, but AMD has been doing that on their CPU chiplets for a while.
Megadrive1988
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So PS5 generation would be starting with a base 10.28 TFLOPs and 8/16 Zen 2 cores at upto 3.5 GHz (but lower GPU TFLOPs at the same time, probably). Still, PS5 is far more powerful than Microsoft's Lockhart / Series S base, and more powerful than many masses of low-end gaming PCs. PS5 Pro / PS5 Cloud could offer multi SoC support for games and more RAM/higher memory bandwidth / HBM2e ./ HBM3 etc.
It's more promising than the GSCube was in the PS2 generation
It's more promising than where CELL ended up during the middle and late part of the PS3 gen, nowhere, a dead end.
It's more promising than the GSCube was in the PS2 generation
It's more promising than where CELL ended up during the middle and late part of the PS3 gen, nowhere, a dead end.
Terrible idea. The high-end console will clearly be held back by the "light" console. /s
Dynamic clocks + dynamic voltage to reduce power consumption based on registers usage. PS5 Pro ? PS5 for cloud ?
(Cloud ?) users will be able to have higher clocks if they pay more. You can't invent that stuff. Pay to overclock.
, I can just remove one wardrobe to make it fit in my gaming room....Megadrive1988
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I'm guessing a PS5 Pro in 2023 would get Zen 4 based CPU and RDNA 4 based GPU.,
8 cores/16 threads, much higher clocks (4.5 GHz systaubed)
GPU 72 RDNA CUs, split over 2 Chiplets 2.5 GHz sustained clocks. 24 GB HBM3 at ~1.5 TB/sec give or take (using 2048-bit bus for ease of manufacturing)
8 cores/16 threads, much higher clocks (4.5 GHz systaubed)
GPU 72 RDNA CUs, split over 2 Chiplets 2.5 GHz sustained clocks. 24 GB HBM3 at ~1.5 TB/sec give or take (using 2048-bit bus for ease of manufacturing)
itsmydamnation
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practically speaking sfp28 or qsfp 28 DAC would be the obvious choice. thats 25/100 Gbps in a very cost effective solution. if that isn't enough PAM encoding can be used to get to 50/200gbps. 400Gbps ethernet uses QSFP-DD which is PAM with more active pins. But the question is how will it work as a cluster using some sort of RDMA, some soft of master, slave etc?
D
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