PlayStation 4 (codename Orbis) technical hardware investigation (news and rumours)
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I think that would be part of the Softbridge chip.
The video encoder is in the APU.
"Gaikai tech" is just marketing fluff. It's the I/O controller with SATA and USB connectivity, misc I/O stuff, maybe some timers and whatnot used for internal purposes and the fabled ARM aux CPU core, video and audio cocecs and so on. It has things which do not strictly have to be on the main APU, and is typically fabricated in an older silicon process (which would be 40nm in TSMC's case.) It needs no heatsink because its power useage is low.
Many PCs need heatsinks on their I/O chips due to massive amounts of on-board I/O which sucks quite a bit of power, but PS4 has so little of that that there appears to be no need.
Many PCs need heatsinks on their I/O chips due to massive amounts of on-board I/O which sucks quite a bit of power, but PS4 has so little of that that there appears to be no need.
Indeed, you can notice on the screenshots and video that there is 6 thermal paste on this heat spreader for the RAM chips and also one thermal "joint" for the APU.
Is it usual for motherboards to be ingeniously passively cooled at the back? (well here the back of the motherboard is at the top of the console
)And I suspect the fact that the motherboard is upside down further helps general cool/heated air flow.
We're talking about the other chip that seems to be only connected to the APU.
Yes - that's the large chip with SCEI stamped on it. The question is about the other chip 'north' of that. To a layman, it looks like most/all of the traces head off to the APU - I'm not sure there's any obvious candidate for what it is?
Well on the PS3 it was similar (size, form, location) of the syscon, an ARM chip responsible of the power managment of the PS3.
So it must fit perfectly with the famous ARM managing low/high power modes and background downloads on the PS4.
If the estimate here are correct (~350mm^2) the APU is quite big.
The 2 jaguar clusters should be tiny, pitcairn is 212mm^2, that leaves a lot of room.
I still wonder if there could be more than 20CUs in Livepool and so more than 2CUs disable for yields, significantly more.
EDIT
From the core section Pitcairn inners are like this:
4x groups each including an array of 3 CUs + an array of 2CUs) With an array defined as a group of CUs tied to the same pool of L1. It seems that AMD wants to keep it symmetrical so for the salvaged part (aka HD7850) they are disabling 1CU per group.
If keeping thing symmetrical is needed for one reason or another, there can't be 4 groups in Liverpool. It has to be 2.
So I wonder if Liverpool could be as such:
2 groups each including:
3 arrays of 4CUs => 6CUs are disabled for yields
or
2 groups each including 2 arrays of 4CUs and one array of 3CUs => 4 CUs are disabled for yields
So there it could be a 22 or 24 CUs design.
Looking at the die size (if the estimates are remotely correct) if should fit easily, actually I would think that there is still room for other things.
I kind of linger to that idea of more than 2CUs being disable because of early comment made by Sony CTO about their SoC packing a lot of design wins wrt to production costs (~ old interview, I don't remember his wording).
Actually if not for the L2 size I could almost wonder if their could be more than 2 Jaguar clusters in Liverpool but 3.
I don't think there are 3 clusters though as it would be weird to disable the cores and parts of the L2 cache which is likely to have high yields. Though I find the idea interesting by self...
Something like that cold have been workable:
22/24CUs in the gpu, 12 cpu cores (3 jaguar clusters).
4/6 Cus are disable on the GPU side.
On the CPU side things could have looked like that.
2 clusters have 3cores enable and access to the full L2
1 cluster has only 2 cores enable and half the L2 => the one reserved for the OS.
That would be 5MB of L2, specs says 4MB => useless speculation.
Though it is extremely unlikely but the following set-up could work with known specs:
2 clusters have 3 cores enable and each cluster has access to 1.5MB of L2 (one bank of the l2 is fused-off). Those 2 clusters handle games and game only.
the third clusters have only 2 cores enabled and access to 1MB of L2 (half the L2 is fused-off). it is reserved for the OS and apps.
Extremely unlikely though, thinking about the comments that were made by one of the CoD dev, such an organization would prevent issues (on the OS side) the same guy alluded to.
Durango has 2 clusters, 6 cores are reserved for games, I guess one cluster (core+L2) is dedicated to game and the other one is more bothering as 2 cores would be working on the game and two on the OS and APPs which could create contention on the L2 cache (may be for memory access too?). Either way the issue is related to the case when the 6 (virtual cores) are folded onto only 4 physical ones, I don't know.
Anyway pretty random speculation, though the SoC is bigger than it should.
The 2 jaguar clusters should be tiny, pitcairn is 212mm^2, that leaves a lot of room.
I still wonder if there could be more than 20CUs in Livepool and so more than 2CUs disable for yields, significantly more.
EDIT
From the core section Pitcairn inners are like this:
4x groups each including an array of 3 CUs + an array of 2CUs) With an array defined as a group of CUs tied to the same pool of L1. It seems that AMD wants to keep it symmetrical so for the salvaged part (aka HD7850) they are disabling 1CU per group.
If keeping thing symmetrical is needed for one reason or another, there can't be 4 groups in Liverpool. It has to be 2.
So I wonder if Liverpool could be as such:
2 groups each including:
3 arrays of 4CUs => 6CUs are disabled for yields
or
2 groups each including 2 arrays of 4CUs and one array of 3CUs => 4 CUs are disabled for yields
So there it could be a 22 or 24 CUs design.
Looking at the die size (if the estimates are remotely correct) if should fit easily, actually I would think that there is still room for other things.
I kind of linger to that idea of more than 2CUs being disable because of early comment made by Sony CTO about their SoC packing a lot of design wins wrt to production costs (~ old interview, I don't remember his wording).
Actually if not for the L2 size I could almost wonder if their could be more than 2 Jaguar clusters in Liverpool but 3.
I don't think there are 3 clusters though as it would be weird to disable the cores and parts of the L2 cache which is likely to have high yields. Though I find the idea interesting by self...
Something like that cold have been workable:
22/24CUs in the gpu, 12 cpu cores (3 jaguar clusters).
4/6 Cus are disable on the GPU side.
On the CPU side things could have looked like that.
2 clusters have 3cores enable and access to the full L2
1 cluster has only 2 cores enable and half the L2 => the one reserved for the OS.
That would be 5MB of L2, specs says 4MB => useless speculation.
Though it is extremely unlikely but the following set-up could work with known specs:
2 clusters have 3 cores enable and each cluster has access to 1.5MB of L2 (one bank of the l2 is fused-off). Those 2 clusters handle games and game only.
the third clusters have only 2 cores enabled and access to 1MB of L2 (half the L2 is fused-off). it is reserved for the OS and apps.
Extremely unlikely though, thinking about the comments that were made by one of the CoD dev, such an organization would prevent issues (on the OS side) the same guy alluded to.
Durango has 2 clusters, 6 cores are reserved for games, I guess one cluster (core+L2) is dedicated to game and the other one is more bothering as 2 cores would be working on the game and two on the OS and APPs which could create contention on the L2 cache (may be for memory access too?). Either way the issue is related to the case when the 6 (virtual cores) are folded onto only 4 physical ones, I don't know.
Anyway pretty random speculation, though the SoC is bigger than it should.
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You are right, it is confusing. But I also found Cerny's words confusing.
what does essentially really mean for Cerny? why not simply: the custom chip is (in) the southbridge ?
So now Cerny acknowledges 2 different entities? The embedded CPU and the Southbridge?
What I do presume is that essentially means that the general concept of Southbridge (as in PC terms) is comprised of 2 individual chips, the good old southbridge and ARM low/high power/background download chip. But I may be wrong and it is only a supposition.
A.k.a. system-on-a-chip.
Ah, yes I understand now. Well, it could be anything really, especially when not able to read the label on the chip, which wouldn't necessarily be helpful to begin with as it's not uncommon for chips in consumer devices to either not be standard parts, or are relabelled standard parts to deliberately obfuscate. Apple loves to put their own labels on chips in their iThings for example.
Theoretically it could be a small FPGA implementing glue logic and miscellaneous bits and pieces to reduce the parts count on the mobo, which could explain the clean appearance of the board. It doesn't have to be a large piece of silicon, as it is a PQFP chip package its size is highly dependent on the number of pins along its edges. The actual die inside could be pretty tiny. Could also be some kind of PC-related, more-or-less vestigal hardware (as the APU is x86-derived.) SuperIO/LPC bus controller chip maybe... *shrug*
And, without knowing where traces on other layers of the boards go, it's hard to say what connects where. After all, we only see what's going on on the topmost layer...
Our estimates of the XB1 APU were high (~410mm^2 vs the MS number of 363mm^2), since we are using the same techniques maybe we are overshooting again?
D
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Technically he's right. We're used to the 'southbridge' being a single purpose chip but southbridge generally refers to the set of slower I/O controllers and functions paired with hard/soft interrupts to support their use. It's just that in the case of PS4, Sony have paired the southbridge functionality with the secondary processor (likely an ARM core running TrustZone) in a single chip.
This configuration is becoming increasingly more common where it's impractical to put an ARM core onboard the main CPU package.
If it's the same overshooting (0.5mm around the edge) that would make it 310mm2 ?
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