This topic is filled with much (read: all) speculation and totally groundless speculation that's akin to randomly picking a number out of a hat. I can't understand why people don't atleast try to get some data points to form an approximation that's atleast in the same ballpark as reality -- as this took me 10minutes using Google and MatLab -- but I distress.
As of April, 2002, this
report from UC-Berkley on the costs associated with 300mm PD-SOI substates (both processing and material) pegs the cost of an SOITEC
Unibond wafer at $1800/wafer and their competitor, Ibis, offering their
SIMOX at $1300/wafer in low-volumes and $700/wafer in high volumes.
It also contains a processing cost curve which, for our purposes, we can assume is approximated by a logarithmic decline, and that as wafer production increases it'll follow this rate. But, since people can disagree with this, I'll stick to their explicit data points of $250 processing costs per a volume of 100K wafers and $450/10K wafers. It's been
stated that when looking at production volume in the long-term, Sony's Fab2 (SOI lines) at Nagasaki will have a net production of 15,000 wafers/month, OTSS at Oita has a stated volume of 12,500 wafers/month, and an unknown volume from IBM's E.Fishkill lines. Needless to say, it's obvious that when summed over the longterm, the production costs collapse to a level bounded by the $200 value (or below).
So, knowing this we can make some reasonable assumptions based on the actual costs and physical aspects which influence costs (Jvd, transistor counts are irrelevent when modeling this abstractly, you might want to stop repeating that). We can state the following:
- 300mm wafer has a theoretical area of 70,685mm2.
- Wafer area usage, intrinsically, isn't 100% effecient
- Cell-DD2 has an area of 235mm2
If we assume a usable area per wafer effeciency of 80%, that yeilds 56,548mm2 of usable space. Enough space to fit 240 Cell-DD2's @ 100% effeciency. At the the following yeilds:
- 90% - 216
- 80% - 192
- 70% - 168
- 60% - 144
- 50% - 120
- 40% - 96
- 30% - 72
- 15% - 36
- 10% - 24
Using the above listed costs per SOI wafer(SOITEC & high-volume SIMOX) and a static processing cost of $300/wafer, the cost for a singular Cell-DD2 is:
- SOITEC; 2003 prices per yeild:
90% - $9
80% - $10
70% - $12
60% - $14
50% - $17
40% - $21
30% - $29
15% - $58
10% - $87
- SIMOX high-volume, 2003 prices by yeild:
90% - $7
80% - $8
70% - $9
60% - $11
50% - $13
40% - $16
30% - $22
15% - $44
10% - $66
EDIT|PS. Please PM or repond for any numerical errors or suggestions. My suggestion is that whomever stated a >$130 cost/IC needs to stop freebasing.
