NVIDIA GF100 & Friends speculation

It was an ironic remark to the speculation that NV drivers could be exceptional immature at launch. Which is highly unlikely considering that they even had working A1 samples. Obviously drivers for a new generation will have growth potential, but I see no reason why the launch drivers should be worse than usual.
Yeah, that claim is patently ridiculous. There is simply no reason for them to not have launch drivers that are as good or better than their previous launches. Even if, as I claim, the work before launch is less efficient than work after launch, they still have had some more time to work on the drivers, and their launch drivers for the past few architectures have been, if anything, getting better with each new generation.
 
I don't know about whether Nvidia didn't double up on vias (nothing stated either way so I have little to say about it).

Nvidia's high amperage/low voltage design "mistake" as described is may be more of a mistake of degree, if it is a mistake.
The need for ever more clean amps at lower voltages is not really new. I was under the impression that one of the reasons GPU boards have all that power regulation circuitry is to step down from the high voltages at the PSU rails to a sane supply voltage and adequate amperage for a mass of twitching fine-geometry transistors.
I believe there was talk about this tension between voltage and amps when Cell was first being introduced.
Perhaps Nvidia's mistake was the extent it was taken to, not so much that it isn't what everyone else is doing.

As for layout changes fixing problems, I got the impression there were two problems Charlie was saying layout would fix. One was how fuse-off granularity was so broad, and the other was changing layout to better account for variation.

Changing the former would strike me as being a design change, as it would need reworking the way the rest of the design assumes the ALUs and data paths are connected.
Changing layout to correct for variation? I don't know enough. My first guess would be to move the fast clock regions to a more concentrated region, so that they are in an area with similar variability.
Other ways of correcting for it might require circuit changes (AMD in the past has disclosed various circuits tuned to correct for variation for its CPUs), but maybe I'm fuzzy on what layout means in this context.
 
I know the higher end parts are the big news. But how about the lower end parts. Anyone hear anything about those ?

I think lacking lower level parts that sell in high volume for dx 11 is a bigger problem than not having a high end out. For every 1 5870 sold I'm sure ati sells 5 or so 5670s . The longer these low end parts go unmatched by nvidia the less of an advantage any increases in performance nvidia might have become as developers target the larger install base of dx 11 chips.
 

That guy is a loose canon, if there ever was one :p

Did he create a similar amount of ruckus during the NV30 days?

Either way, somebody or the other is gonna get a massive black eye, not long from now. And it wouldn't be the first time for either NV or CD.

Other ways of correcting for it might require circuit changes (AMD in the past has disclosed various circuits tuned to correct for variation for its CPUs), but maybe I'm fuzzy on what layout means in this context.

My guess is that it is just CD's way of angling for a full silicon respin. Even he does not understand what exactly the silicon respin is supposed to be for.

Charlie said:
Nvidia on the other hand did not do their homework at all. In its usual 'bull in a china shop' way, SemiAccurate was told several times that the officially blessed Nvidia solution to the problem was engineering by screaming at people. Needless to say, while cathartic, it does not change chip design or the laws of physics. It doesn't make you friends either.

Considering that it is an accepted practice to ignore some of the fab's design rules/hints to optimize your chips, the present failings could just be immaturity on nv's process team's part. After all, this is their first large chip at cutting-edge process in a long time.
 
I actually thought the article wasn't bad , he kept his "Nvidia is doomed" tone down , that allowed me to enjoy the article .

However I personally think that the situation can not be that bad !

One more thing , anybody else noticed how the Vias and transistor variation problems just started to show up now , right after Anandtech's story ? the justification of them being secret doesn't add up !

If they were so secret and Charlie knew about them long time ago, then why he didn't tell about them ? for the sake of ATi perhaps ?

I would be more than welcome if somebody corrected my presumably naive thinking .
 
I actually thought the article wasn't bad , he kept his "Nvidia is doomed" tone down , that allowed me to enjoy the article .

However I personally think that the situation can not be that bad !

One more thing , anybody else noticed how the Vias and transistor variation problems just started to show up now , right after Anandtech's story ? the justification of them being secret doesn't add up !

If they were so secret and Charlie knew about them long time ago, then why he didn't tell about them ? for the sake of ATi perhaps ?

I would be more than welcome if somebody corrected my presumably naive thinking .

He could have simply signed an NDA
 
I actually thought the article wasn't bad , he kept his "Nvidia is doomed" tone down , that allowed me to enjoy the article .

However I personally think that the situation can not be that bad !

One more thing , anybody else noticed how the Vias and transistor variation problems just started to show up now , right after Anandtech's story ? the justification of them being secret doesn't add up !

If they were so secret and Charlie knew about them long time ago, then why he didn't tell about them ? for the sake of ATi perhaps ?

I would be more than welcome if somebody corrected my presumably naive thinking .

Because he has no informations.
He also claimed that tesla would be a 512 part and nVidia missed their clocks. Or that tessellation will kill the performance because of the "software" implementation. Or that Cypress will be faster in DX11 than Fermi...
 
One more thing , anybody else noticed how the Vias and transistor variation problems just started to show up now , right after Anandtech's story ? the justification of them being secret doesn't add up !

If they were so secret and Charlie knew about them long time ago, then why he didn't tell about them ? for the sake of ATi perhaps ?

Dave Baumann alluded to the via issue a month ago in this thread.
 
TSMC has had via issues before. The first case I know of is back at 130nm or 90nm.

And while you can go ahead and ignore some design rules, you need to be very very very careful. Everyone I've ever talked to about this was very clear - TSMC has the loosest design rules out there, if you ignore them, do so at your own peril. And pay close attention to their recommendations, or you're likely to be sorry.

David
 
Or he could have not wanted to have disclosed his source, which might have happened if he spoke up about it.

http://twitter.com/Igor_Stanek

RT @madciapka: @Igor_Stanek there was any sign of credibility before that? I don't think so :) :me right, you are right..

RT@RS_Borsti I want to see how he is going to explain his article in March.... looks like biggest lie and mistake of his life :)

RT @RS_Borsti: Oh Charlie... that just another hilarious post me: I think with this post Charlie totally destroyed his credibility :)

March confirmed? And Charlie off-base? Or simply more bluffing?
 
RV740 was delayed by 6 months+ due to 40nm issues and ended-up hot, "slow" and bigger than intended.

NVidia saw the same problems. GT214 had enough problems that part of NVidia's solution was to make it smaller: less multiprocessors/TMUs - hence GT215.

And of course GT212 was just killed.

Neither of those solutions actually helped GF100's implementation in any way, it seems. NVidia prolly should have scaled GF100 down to a 256-bit bus and 12 multiprocessors/3 GPCs, but chose to continue on regardless.

The extra vias trick might not have been an option for GF100 - we don't know how much extra area that would have resulted in.

The bizarre thing about all this is that NVidia has not delivered a sizeable chip on time since G80 - it really should have been obvious internally that they were on the losing end of the 80:20 rule.

Maybe they thought Win7 was going to launch in spring 2010?

Jawed
 
At this point, I think Nvidia should be looking to their own credibility before they start criticising others. They are not even in the position of letting the product speak for itself.

I think it's hilarious that Nvidia PR is using Twitter as a medium. I'm not sure which aspect of Charlie's article they're mocking though since he said a lot of stuff in there.

Neither of those solutions actually helped GF100's implementation in any way, it seems. NVidia prolly should have scaled GF100 down to a 256-bit bus and 12 multiprocessors/3 GPCs, but chose to continue on regardless.

Tesla is a consideration there as well, something AMD didn't have to worry about. Also, it could just be due to their infamous arrogance. If it's true that the downmarket parts haven't even taped out yet then the pain isn't going to ease for a while. Would the GF104 team have started on a base layer respin once GT2xx/GF100 issues became evident early last year? Or would they have just sit back and wait for TSMC to fix all their problems for them?

Maybe they thought Win7 was going to launch in spring 2010?

Why would they? They would certainly have been privy to the same info that AMD was and they targeted fall 09. Given the problems at TSMC it's clear that any deadline was badly blown.
 
It's funny he mentions credibility after the fake cards fiasco last year. Talk about pot calling kettle black.

I've read the article and, Charlie's bias notwithstanding, looks pretty bad for NV if they indeed have so many problems with GF100. I'm not sure what conclusions to draw from it, I find it hard to believe that they made such a poor job.
 
Stanek also promissed availability in late November 09, late he promissed reviews in late December etc. so from my perspective Charlie has higher credibility than him.

Oh he did? Got a link? I want to see if he was as smug then as he is being now.
 
Tesla is a consideration there as well,[...].
What do you mean by that? The functionality/new features + the vastly better DP are more important than ~20-30% performance.

If it's true that the downmarket parts haven't even taped out yet then the pain isn't going to ease for a while.
I'm pretty sceptical that they haven't taped. The architecture works: NVidia's problem is solving the 40nm-specific problems - which should be easier because they're smaller chips, plus 40nm has had 1 year to mature - AMD's done a lot of legwork with TSMC, etc.

Would the GF104 team have started on a base layer respin once GT2xx/GF100 issues became evident early last year? Or would they have just sit back and wait for TSMC to fix all their problems for them?
Depends what GF104 is. It should be TSMC's next process, i.e. 28nm. It should have been ready for production at the end of this year and TSMC is saying that it will be.

Why would they? They would certainly have been privy to the same info that AMD was and they targeted fall 09. Given the problems at TSMC it's clear that any deadline was badly blown.
Win7 was pulled forward a fair bit. NVidia may have originally planned for there to be a comfortable margin between 40nm being production ready and having to get GF100 on the market. i.e. GF100 might have had its tape-out brought forwards by 1 quarter+ (though NVidia looks like it needed to pull it forwards by 2 quarters, hence all the angst a year ago about the fake tape-out rumours).

http://www.informationweek.com/news/windows/operatingsystems/showArticle.jhtml?articleID=207100040

Obviously, January 2010 isn't as late as spring, but AMD was aiming for August 2009 for Evergreen, ~2 quarters ahead of "the accepted wisdom" for Win7 launch. Though you might argue that 1 quarter could have been expected to have been lost to a metal spin after that. Is Cypress A1?

http://www.techreport.com/articles.x/17618/2

Shows week 17 engineering sample, which is end of April (XBit Labs has one from 2 weeks earlier, Bit-tech 2 weeks later and iXbt from week 24 - all engineering samples over a period of at least 9 weeks).

Jawed
 
Back
Top