NVIDIA GF100 & Friends speculation

Discussion in 'Architecture and Products' started by Arty, Oct 1, 2009.

  1. jimmyjames123

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    Well the ALU/TEX ratio will be increasing dramatically from GT200, per comments on evga forum. So yes, the number of texture units will be going down (presumably to 64).
     
    #621 jimmyjames123, Jan 18, 2010
    Last edited by a moderator: Jan 18, 2010
  2. John Reynolds

    John Reynolds Ecce homo
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    Guys, please remember the Charlie love/hate thread is that way ------->

    To the person who linked Charlie's article in this thread upstream, if I could come across the internet and donkey punch you in your twig 'n berries right now, I would. Sheesh.
     
  3. ChrisRay

    ChrisRay <span style="color: rgb(124, 197, 0)">R.I.P. 1983-
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    Well the article was good for a laugh I guess. I know me and a few others enjoyed. I guess he can believe what he wants to believe. Performance will speak for itself.
     
  4. Ninjaprime

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    Well, its past 9pm, anyone have anything interesting to report?
     
  5. {Sniping}Waste

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    Its just slides with info that been going around for the last 3 week. There is no reviewer benchmarks just slides from NV that say what they say the performance will be. Its more a waste of time. If reviewers had cards to work with and put there finding is one thing but this is just highly controlled info with no real independent reviewer data.
     
  6. John Reynolds

    John Reynolds Ecce homo
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    Yea, the lack of consumer-related info on things like different board configs, clock speeds, price, power gobbling, etc., is disappointing, but NV is most likely still getting a handle on this beast's yields.
     
  7. Ninjaprime

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    Interesting:
    So, 64 texture units but they are effectively clocked twice as high. Not too shabby.

    At least thats how I read it, they are clocked at the shader hotclock?
     
  8. rjc

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    A few days ago on chiphell tomsmith(post #66, talking about Fellix's numbers posted here previously):
    ie Current cards at 650Mhz/448 shaders are at the previously quoted performance figures with scope to increase frequency a little. 512 shader product will require a retape.

    So a long wait still..... :cry:
     
    #630 rjc, Jan 18, 2010
    Last edited by a moderator: Jan 18, 2010
  9. Brent

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    Don't know how the clock domains are going to work out, only that the Texture Units do not operate at the GPU/ROP clock, they will be higher, if they match Shader clock I do not know yet. No information on clock speed domains.
     
  10. {Sniping}Waste

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    No that's not it. The TMUs are clocked at half the speed of the Cuda cores. It the CC are at 1.5gig then the TMU's are at 750mhz. The GTX285 TMU's is at 600mhz. I think the the CC target speed is 1.5gig but hearing it might be 1.2gig.
     
  11. Ninjaprime

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    I wonder how the 448 shader thing works with a raster engine per 4 SMs. One just has a lot of free time? Or is it two have a little free time? Seems like the would more likely go for 384, disabling an enitre unit.
     
  12. Ninjaprime

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    I see, not as good as I thought, but still better than just 64 TMU's at the core clock... maybe. Didnt that one article out of china say they were going with a 2:1 locked clock for core/shaders now though?
     
  13. DemoCoder

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    4 triangle setup units, and 16 fixed-function DX11 tessellation stages. @600Mhz, that would be 2.4 billion tris/second. Each tessellator can produce an amplification of up to 64X, and there are 32 ALUs per unit for domain shading. By doing the work now of finally parallelizing the last bits of fixed function pipeline hardware, it looks like have more future flexibility for scaling. It's almost true multicore now. It might be that the ratios of setup to tessellator to ALU could be revised for the future (e.g. 2 SMs per raster engine, or 8)

    I actually read this as the exact opposite of Charlie. The hard work was splitting up the previously monolithic units. Adjusting where you locate these units and the ratio of them is easier. The idea that they can't scale this up in the future seems like FUD.
     
  14. XMAN26

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    It reads like that scaling it down has been made extremely easy. They could use GF100 for the 448 and 512SP parts, maybe even a 384 part. redo the layout and use it for 256 and 192 binned parts, rearrange and then have 1 skew layout for 128 and a layout for a 64. Obviously the top to bottom would look like this

    Single GPUs
    Highend
    512SP
    448SP
    384SP(Use this for dual GPU after you remove 128SP and rearrange the die package)
    Midrange
    256SP and 192SP
    Mainstream and entry lvl
    128SP and 64SP

    Nvidia, please end this senseless need to only give entry lvl people 16SPs and call them gaming cards, let be reasonable for once, make the bottom end 64SPs.
     
    #636 XMAN26, Jan 18, 2010
    Last edited by a moderator: Jan 18, 2010
  15. sc3252

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    http://anandtech.com/video/showdoc.aspx?i=3721&p=2
    "Finally, texture units are now tied to the shader clock and not the core clock. They run at 1/2 the shader clock speed of GF100."

    I wonder how much more texture performance its going to have than gt200. can't be much if it is indeed half the hot clock and only 64.
     
  16. sc3252

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    yes, but don't they always say its going to be easy scaling it down?
     
  17. itsmydamnation

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    i think charlie was saying that tessalation performace is tied directly to shader utilization so on lower parts tessalation could become a bottleneck where as on an ATI card the tessalation performace is constant across the whole product line.

    Apart from that in general i agree it seems to be "easy" to scale each part as needed. apart from setup didn't AMD go down this path with R600 and then revert to a more fixed configuration for RV770? I wonder what the trade offs are.

    edit: yes i know ATI had more fixed function parts.
     
  18. trinibwoy

    trinibwoy Meh
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    Which is what we've always known it was going to be. Reviewers can't have cards until Nvidia does ;) What they're trying to do is impressive but it's still gotta be put to the test. I'm really curious to know how they maintain triangle order across the chip with geometry processing so widely distributed.
     
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