NV48 350mil transistors on .11 lk.

[DOGMA1138]

won`t it increas the die size buy approx 50%?
http://www.xbitlabs.com/news/video/display/20041220031126.html

 

[MuFu]

Where did you get the "350 million" figure from and *what* will increase the die size by 50%?

TSMC do not offer a 0.11u low-k process. Besides, look...

http://www.beyond3d.com/forum/viewtopic.php?t=19163
http://www.beyond3d.com/forum/viewtopic.php?t=19069

 

[DOGMA1138]

NV40=220 mil + 100-120 for 8 more pixel pipes and 8-6 vertex shaders + 10~ for fixing the video encoder etc. you get 350~ mil transistors. thats my guess any way 8)

 

[MuFu]

Ah, I see. The die size will probably remain about the same if they decide to increase the number of pixel quads/VS units (since they're supposedly switching to 0.11u).

Interesting that there's barely a mention of 0.11u on TSMC's site. I wonder if what we've seen from NV43, RV410 and R430 is representative of the best they have to offer at that node. Perhaps a more performance-oriented 0.11u process + a Vcore bump + lean binning is what nV will be using for their next high-end product.

 

[DOGMA1138]

the move from .13 to .11 wont make things much diffrent IMO. the R430 and R480 die is the same+-. the move to 0.09 should allow you to allmost double the transistor count w/o any major die space increasment AFAIK.

 

[MuFu]

R430 is about 20% smaller than R480. I suspect you're right about 0.09u though.

 

[Kaotik]

You can indeed fit pretty much twice the transistors with 90nm to same space compared to 130nm

 

[Kanyamagufa]

You can indeed fit pretty much twice the transistors with 90nm to same space compared to 130nm

Sorta at a loss for how this is possible...

Logically (I think...), one might think that it would be 65nm that could do that, not 90nm.

But please explain, I'm extremely interested.

 

[MuFu]

130nm=>90nm ~= 30% reduction in one dimension.
130nm^2=>90nm^2 ~= 50% reduction in area.

Bit of a crude way of looking at it but I think it holds in practice.

 

[phenix]

130nm=>90nm ~= 30% reduction in one dimension.
130nm^2=>90nm^2 ~= 50% reduction in area.

Bit of a crude way of looking at it but I think it holds in practice.

What about the other dimension? 8)

 

[DOGMA1138]

the die is "flat", only 1 layer of transistors on a silica base AFIAK.

 

[MuFu]

130nm=>90nm ~= 30% reduction in one dimension.
130nm^2=>90nm^2 ~= 50% reduction in area.

Bit of a crude way of looking at it but I think it holds in practice.

What about the other dimension? 8)

The ASICs we're talking about have one layer of transistors, the layout of which is two dimensional only. Above that it's just metal contacts and vias (AFAIK) so we can disregard the third dimension when talking about transistor counts. For a given process they're relatively correlatory as far as die area vs transistor count goes.

 

[aaronspink]

The ASICs we're talking about have several layers of transistors, the layouts of which are two dimensional only.

Just a point of correction. There is only a single planar layer of transistors. There are multiple metal layers which are used to route between the transistors and deliver clock and power

Aaron Spink
speaking for myself inc.

 

[MuFu]

Shit that's right, thanks. Been a while since I did EE. :?

 

[3dilettante]

You can indeed fit pretty much twice the transistors with 90nm to same space compared to 130nm

Sorta at a loss for how this is possible...

Logically (I think...), one might think that it would be 65nm that could do that, not 90nm.

But please explain, I'm extremely interested.

You can work this out in reverse.

With squares, doubling edge length means quadrupling area. To double area, you just need to increase the lengths of a square's sides by the square root of 2. You could only fit half as many transistors of doubled area in the same space as transistors of standard size.

Assuming a 90 nm processor transistor is a square (they aren't really, but this should approximate), then that transistor scaled to 130 nm would mean a an increase in dimensions of 130/90 or ~1.444.
The square root of two is ~1.414.

This means a 130 nm transistor has a roughly doubled area of a scaled 90nm version, assuming everything scales the same between the process, which is not true but I think it's not as important as the general relationship.

 

[Coz]

NV40=220 mil + 100-120 for 8 more pixel pipes and 8-6 vertex shaders + 10~ for fixing the video encoder etc. you get 350~ mil transistors. thats my guess any way

The difference between NV40 (16-pipe, 6xVS, 222M trans) and NV43 (8-pipe, 3xVS, 143M trans) is 79 million transistors. Some of those 79M are for the extra 128-bits in the NV40 memory controller so let's call the extra 2 quads and 3xVS about 70 million transistors. Add that to 222M and you get 292 million transistors for NV48 assuming the only difference between it and NV40 is a couple of quads and +3xVS (I don't see why you *need* to add transistors to fix the video processor).

That's at the high-end of what to expect with NV48 so I would imagine it'll be plenty less than my estimate in reality and waaaay less than 350 million (unless we see a whole bunch of extra stuff over and above what I've described).

 

[Robbitop]

10 Mio for the Memorycontroller? Are you crazy?
I'd say a Quad should cost around 20-30 Mio Transistors. A MIMD VS Unit should be under 10 Mio Transistors per each.

Maybe they want to make the pipelines deeper (more ALUs per Quad).

 

[Coz]

10 Mio for the Memorycontroller? Are you crazy?

Well, that was just a WAG (Wild-Assed Guess) on my part but it seems that you actually know the real answer!

So mein guter Freund, how many transistors make up the memory controller on the NV40.......exactly?

 

[Robbitop]

So mein guter Freund, how many transistors make up the memory controller on the NV40.......exactly?

don't try german ..sounds quite cruel

Look at the NV34 or the RV250. Both got around 40 Mio Transistors. And both got an 128 Bit DDR interface. 10 Mio would be way too much.
I guess an Mem interface ist quite "cheap". Dunno exact numbers but I guess the wohle 256 Bit DDR Interface won't cost 10 Mio ;-)

 

[Coz]

Look at the NV34 or the RV250. Both got around 40 Mio Transistors. And both got an 128 Bit DDR interface. 10 Mio would be way too much.

Good point! I yield to your superior knowledge good sir.