it's been a while since I read something on the topic,the article by David Kanter @ realworldtech where enlightening it should be worth another read (for those interested it's here).Well, fwiw, it's one reason why the intel GPU has any decent speed at all (access to cache). The problem will be seeing how this scales up to a beefier core because you'll want a lot more cache.
I'm not to discuss technicality with you (or not too much) but it's a bit of an unfair statement to what Intel achieved with their GEN6 GPU. They improved a lot their architecture even though texture filtering is a weak point. I'm not sure that better performances are due to access to the L3 (only, they included a lot more fixed fuction hardware too for example). D.Kanter thinks that for now the main benefit is for Intel driver team
... lulz...
In regard to scaling it looks like Intel is paving the way for future improvements with Ivy Bridge as the GPU with have it's own share of the L3, if I get it right they plan to connect more of their "data ports" to this part of the L3 without creating traffic on the chip main ring bus. Still we don't know how much L3 the GPU will embark. Now SnB GPU can take as much as 2MB of the L3 which is indeed a lot (even though we don't know if it's happening during games), I would be surprised if Intel goes with this much L3 for IB.
The goal of this post is subliminal, if I see a B3D test of the Intel GEN6 GPU it will have succeed
More seriously, I was reading stuffs on SoC and find this interesting as an example of CPU GPU integration and how they can share data in a proper implementation (sad but it looks like AMD lag significantly behind both ARM and Intel, it may become more obvious once those too have direct compute5 enable part).