anexanhume
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No, but when comprising architectures from the same vendor, it speaks directly to how wide and the clock speeds of a specific device.
Next Generation Hardware Speculation with a Technical Spin [pre E3 2019]
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I covered that in the post above yours. I'm not saying the metric is useless, I'm saying people aren't applying it correctly.
I’m referring to performance in general, specifically the performance delta to the current gen.
Which ever metric you want to use.
Just going Ryzen to Jaguar makes for a fairly significant performance delta.
In a $400 console only ~$250 goes into the cpu & gpu & memory & cooling. $100 more lets you put in $350 into cpu & gpu & memory & cooling. A 40% higher budget for the silicon heart of the system.
If Anaconda and PS5 do launch with that price difference we could be seeing a +30% difference in FLOPS similar to what we saw on the PRO vs X1X.
If Anaconda and PS5 do launch with that price difference we could be seeing a +30% difference in FLOPS similar to what we saw on the PRO vs X1X.
And in a total arbitrary way too. People stating they won’t accept anything below 11.5 TF. Like, what the teraflop are you talking about? What does 11.5 TF even mean in reality, compared to 10, 9 or 8?
They aren’t arbitrary though. Those numbers are all around ~2x Scorpio. 7,8,9 are too close to Scorpio to be justifiable in their minds for next gen. Thus, perhaps why Scorpio was a problem for Sony. It’s not a technical problem or performance problem necessarily, but it’s certainly a marketing problem. And if you don’t have a special feature set either it’s going to be a harder to differentiate.
I’m not going to say they’re wrong I’m thinking this way, but as discussed, it’s not how it works. TF is a single metric in which we assume the whole card will build itself around. Unfortunately some architectures have a much easier time at saturating their hardware than others and this is why the metric is a flawed number to use.
For us we should be thinking costs, die size, TDP, storage memory and feature sets. I think if we’re honest with a $399 price point, as many have put out there, we need to start looking closer to 7.5+TF - because lets be honest, 10-12TF needs to be beefed up everywhere to get full extraction.
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anexanhume
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We can almost certainly expect the APU to cost more but the RAM could be less if they’re using only 8 or 12 physical chips as opposed to 16.
Ram seems to be droping steadily on dramxchange, went from $9/GB to less than $6/GB in a few months and it's expected to continue to drop.
I am even hopeful 24GB gddr6 is possible for 2020. But maybe they would still prefer 16GB and put more money in the SoC. I suppose 50% more on that 7nm silicon would be a bigger gain than 50% more memory, if we expect the game size would only grow to 100GB, it's not like assets will explode in size and we also have a strong possiibility of flash cache or SSD to help.
anexanhume
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Agreed. 18GB is also a possibility with a 384-bit bus.
I saw a 120GB SATA SSD for $20 this morning, BTW.
If they could move the OS reserve to a LPDDR4 pool that would certainly free up additional room and reduce the need to have to go to something like 20-24GB of expensive RAM for everything.
With the GDDR memory being exclusively for games the developers still get to deal with a unified memory pool.
With the GDDR memory being exclusively for games the developers still get to deal with a unified memory pool.
It depends what the cost difference is between lpddr and gddr, I don't think a split memory is worth it on an SoC, having to add ddr controllers used only by the OS. If they had silicon area to spare for more controllers, they might as well add more gddr controllers and keep it unified and increase bandwidth.
I liked their implememtation of the SB memory as an app swap space. It doesn't cost additonal memory controllers on the main SoC since they used more or less an off the shelf ARM as a south bridge (maybe a bit modified, but it can't be an expensive chip). And they needed a SB anyway with enough pcie lines going to the main SoC. But it's not fast enough to run the OS and apps through that tiny pcie bus.
I think I proposed this before:
4GB DDR3/4 on the SB for app/game context swap space
8 lanes Pcie 3 (swap 4GB in 1 sec) also needed anyway if they want some SSD
16GB GDDR6
Only 1GB fully reserved for the OS
So with the game paused the Apps and OS can use 5GB and games can have 15GB, 3x current gen.
Everything runs full speed except the 1 second delay to pause and maybe a bit more to resume.
I liked their implememtation of the SB memory as an app swap space. It doesn't cost additonal memory controllers on the main SoC since they used more or less an off the shelf ARM as a south bridge (maybe a bit modified, but it can't be an expensive chip). And they needed a SB anyway with enough pcie lines going to the main SoC. But it's not fast enough to run the OS and apps through that tiny pcie bus.
I think I proposed this before:
4GB DDR3/4 on the SB for app/game context swap space
8 lanes Pcie 3 (swap 4GB in 1 sec) also needed anyway if they want some SSD
16GB GDDR6
Only 1GB fully reserved for the OS
So with the game paused the Apps and OS can use 5GB and games can have 15GB, 3x current gen.
Everything runs full speed except the 1 second delay to pause and maybe a bit more to resume.
How exactly did you plan to put 18 GB of mem and 384-bit bus together?
anexanhume
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The GDDR6 spec allows for 12Gb die.
DmitryKo
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Why use LP (low power) DDR? That's a different signalling protocol, and the key design point is deep-sleep power states for vertically-stacked mobile SOC (system-on-chip) die.
They could as well use stacked GDDR6 or DDR5 (and maybe even HBM) right on the APU package, as soon there will be a choice of compatible packaging and 3D stacking technologies - such as FOWLP (Fan-Out Wafer-Level Packaging) discussed earlier in this thread, essentially a Redistribution Layer (RDL) of several copper wire-bonding layers encapsulated in hard resin, either produced directly on wafer (chip first) or pre-fabricated and attached to several dies with micro-bumps (chip last).
These would supersede the SOC paradigm with System-in-Package (SiP), a heterogeneous integration of smaller processing dies, which could use different process nodes and/or manufacturers, interconnected directly on a package - as opposed to current design and manufacturing process for an integrated SOC die, using a monolithic chip on a single process node.
Here is an IEEE presentation with lots of illustrations and STM cross-sections:
IEEE/EPS Chapter Lecture in the Silicon Valley Area
Fan-Out Wafer-Level Packaging for 3D IC Heterogeneous Integration
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Spec allowing something is a far cry from someone actually doing such, if someone announces even plans to do 12 Gb dies then sure but I doubt it
anexanhume
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Or maybe if a customer requested it and had volumes in the tens of millions of die...
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