7nm is a family, not one specific process.AMD already confirmed 7nm, this isn't the baseless section either
For instance for TSMC, 7nm+ is the second generation of 7nm.
Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]
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For instance for TSMC, 7nm+ is the second generation of 7nm.
I'll go ahead and use digital foundry's estimate (taking into account rt hardware) of 44 total / 40 active cus for 350mm^2 and 7nm
https://www.eurogamer.net/articles/digitalfoundry-2019-project-scarlett-spec-analysis
For 7nm+, multiply 44 by 1.25 and you get 55. So I think it would something like 56 total with 52 active.
https://www.eurogamer.net/articles/digitalfoundry-2019-project-scarlett-spec-analysis
For 7nm+, multiply 44 by 1.25 and you get 55. So I think it would something like 56 total with 52 active.
40CU is 251mm2. There are stuff on the Navi 10 die that would be stripped from the console, xfire support, PCIe bus interface, eyefinity, true audio dsp, uvd, vce, etc. I am guessing around 20mm2.
That leaves ~120mm2 (350 - 230) to play with.
Au contraire to what DF said, Zen2 cores are around 60-65mm2 stripped down for an APU.
https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/5
"For Zen 2, a single chiplet is 74mm2, of which 31.3 mm2 is a core complex with 16 MB of L3. AMD did not breakdown this 31.3 number into cores and L3, but one might imagine that the L3 might be approaching 50% of that number. The reason the chiplet is so much smaller is that it doesn’t need memory controllers, it only has one IF link, and has no IO, because all of the platform requirements are on the IO die. This allows AMD to make the chiplets extremely compact. However if AMD intends to keep increasing the L3 cache, we might end up with most of the chip as L3."
64bit phy GDDR6 controller is around 10mm2, assuming we have a 320bit bus. Zen2 cores are around ~60-65mm2. Assuming 20-25mm2 for RT, ~25mm2 left over should be enough for 5-6 dual CUs / or 10-12 CUs.
I expect a 350mm2 chip to have 48 to 52 total CUs, more if they shrink the L3.
That leaves ~120mm2 (350 - 230) to play with.
Au contraire to what DF said, Zen2 cores are around 60-65mm2 stripped down for an APU.
https://www.anandtech.com/show/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome/5
"For Zen 2, a single chiplet is 74mm2, of which 31.3 mm2 is a core complex with 16 MB of L3. AMD did not breakdown this 31.3 number into cores and L3, but one might imagine that the L3 might be approaching 50% of that number. The reason the chiplet is so much smaller is that it doesn’t need memory controllers, it only has one IF link, and has no IO, because all of the platform requirements are on the IO die. This allows AMD to make the chiplets extremely compact. However if AMD intends to keep increasing the L3 cache, we might end up with most of the chip as L3."
64bit phy GDDR6 controller is around 10mm2, assuming we have a 320bit bus. Zen2 cores are around ~60-65mm2. Assuming 20-25mm2 for RT, ~25mm2 left over should be enough for 5-6 dual CUs / or 10-12 CUs.
I expect a 350mm2 chip to have 48 to 52 total CUs, more if they shrink the L3.
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AMD already confirmed 7nm, this isn't the baseless section either
They only confirmed it for PS5 as far as I can remember.
MS did say Zen2 so I am assuming N7P for them too.
What are the possibilities of existing an Hybrid access memory area that both GPU and CPU can feed on "simultaneously" or sequentially without the read and write penalty for some kind of Hybrid RT?
I'm not an expert on this but some of the problems of having a hybrid RT solution that i read about was exactly that. On a shared memory system this could be a much simpler solution if both had direct access.
I'm not an expert on this but some of the problems of having a hybrid RT solution that i read about was exactly that. On a shared memory system this could be a much simpler solution if both had direct access.
Highly likely scarlett will be on the same node. Close to 9/10TF i hope, would be 5700XT level with ray tracing hardware.
I know I said I was skeptical of RDNA2, but with AMD's offical announcement of "future RDNA architectures", I am more open to the possibility of Microsoft using RDNA2.
I am assuming it's easier to back port the RDNA2 RT features to 7nm than to port Zen 2 to 7nm+.
Janne Kylliö
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Is chiplet solution out of the question, cost wise? If not, then you could have mixed process approach, i.e. a 7nm Zen2 CPU chiplet and a 7nm+ RDNA2 GPU on a same chip.
Probably not going by the teaser shot of the Scarlett die.
anexanhume
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Nvm
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Depends on the design. But from what I've seen moving an existing design to a new process is easier than moving a new design to an older processes (assuming mature tools and libraries). Newer nodes can usually hit higher clocks so you may run into a trouble with timing if the new design can't close timing on the older process due to a high clock. That will require some tweaks to the timing paths of the design. But for 7nm / 7nm+ I don't think the changes are that relevant to be a big issue.
There are really two designs: the RTL code which defines the behavior and architecture and then the physical transistor layout. The former shouldn't really need to change unless there are timing fixes needed. The latter will need to be redone anyway for a new chip so moving to a new process can just factored in as part of the new design.
On the CPU side the clocks will be coming down (compared to commercial Zen), so that may allow them to use smaller transistors resulting in denser area and better power. I don't know if they will invest in that, but it would certainly be something that I would investigate.
Megadrive1988
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I don't see why Microsoft and/or Sony could not have RDNA2 (or something close to it) in Holiday 2020 consoles, if they had wanted it.
If PS5 was releasing Nov 2019, then probably not much more than RDNA1, yet both are Q4 2020.
1. AMD Radeon Technology Group is mainly based on their acquisition of ATI more than a decade ago.
2. Xbox 360's GPU (Xenos) design was, AFAIK, finished sometime around early to mid 2004 at the latest and Xbox 360 released November 2005.
3. Xenos was the first time a unified shader architecture was in a consumer product.
4. Nvidia didn't have its own unified shader GPU until G80 / 8800 GTX in Fall 2006. PS3 released near 8800 GTX release, yet RSX lacked a unified architecture.
5. ATI's own unified GPUs for PC (R600 / Radeon 2900XT) did not release until like May 2007.
If unified shaders in GPUs is an analogy to RDNA2, given the timeframes of what happened in the past, I think there's the potential for both
PS5 and Scarlett to have something closer to RDNA2 than current RDNA in current Navi GPUs. Obviously that alone confirms nothing,
but given all the current info we have about 2019-2020 AMD GPU tech, I think its more than possible.
Agree? Disagree?
If PS5 was releasing Nov 2019, then probably not much more than RDNA1, yet both are Q4 2020.
1. AMD Radeon Technology Group is mainly based on their acquisition of ATI more than a decade ago.
2. Xbox 360's GPU (Xenos) design was, AFAIK, finished sometime around early to mid 2004 at the latest and Xbox 360 released November 2005.
3. Xenos was the first time a unified shader architecture was in a consumer product.
4. Nvidia didn't have its own unified shader GPU until G80 / 8800 GTX in Fall 2006. PS3 released near 8800 GTX release, yet RSX lacked a unified architecture.
5. ATI's own unified GPUs for PC (R600 / Radeon 2900XT) did not release until like May 2007.
If unified shaders in GPUs is an analogy to RDNA2, given the timeframes of what happened in the past, I think there's the potential for both
PS5 and Scarlett to have something closer to RDNA2 than current RDNA in current Navi GPUs. Obviously that alone confirms nothing,
but given all the current info we have about 2019-2020 AMD GPU tech, I think its more than possible.
Agree? Disagree?
Panino Manino
Newcomer
We know that Navi is in the works for a long time but...
Well, how much will "Navi 1.2" change, really? Beyond just some tweaks?
And the RT solution was being worked since the beginning? AMD using a "modular approach" could very well mean that the nothing much will change in the design beyond adding the RT block. Of course, if the RT part is something more separate like in Turing and not a more "conventional solution".
This to not mention that Sony and Microsoft may end with two different solutions.
My guess is that "Navi 1.2" will only scale the CU count.
Sony will use a "hybrid" RT approach with little change upon Navi and Microsoft designed custom hardware themselves.
But what makes me more curious in the end is the CPU, if it'll use "Zen 2+", and they'll manage to keep the latency lower than in the desktop.
Well, how much will "Navi 1.2" change, really? Beyond just some tweaks?
And the RT solution was being worked since the beginning? AMD using a "modular approach" could very well mean that the nothing much will change in the design beyond adding the RT block. Of course, if the RT part is something more separate like in Turing and not a more "conventional solution".
This to not mention that Sony and Microsoft may end with two different solutions.
My guess is that "Navi 1.2" will only scale the CU count.
Sony will use a "hybrid" RT approach with little change upon Navi and Microsoft designed custom hardware themselves.
But what makes me more curious in the end is the CPU, if it'll use "Zen 2+", and they'll manage to keep the latency lower than in the desktop.
D
Deleted member 11852
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How much time does that give devs with the new hardware before launch? Are you suggesting push back the launch for a year to 2021, or is RDNA2 a zero-effort advance over RDNA requiring no changes to existing code?
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anexanhume
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They don't have to leverage every benefit day 1.How much time does that give devs with the new hardware before launch? Are you suggesting push back the launch for a year to 2021, or is RDNA2 a zero-effort advance over RDNA requiring no changes to existing code?
If they dont, I'm cancelling my preorders!
Drivers etc all need to be ready. Waiting on RDNA 2 just may not be in the cards if it’s not ready; there is still production time etc and everything else around the console that needs to come together for this to ship; not just the singular APU. RDNA 1 with 2.0 features sounds like a like route that is likely going to be walked. In about 3-4 months time the chips need to be made. That means die tooling needs to be done way before that. Test runs before that etc. All the trials to work out silicon defects etc all need to be worked on to make the launch price economics.
anexanhume
Veteran
You’re assuming all the next gen RDNA 2.0 features won’t see real silicon until sample dies. We already know next gen consoles have sampled their APUs and in all likelihood that includes the TMU based RT hardware.
Comparatively, the consoles need final silicon 16 months after 5700 needed final silicon. Subtract a few months for higher initial volume, but the point stands.
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