Since 2014, some level of adoption was marketed for Steamroller and beyond for x86 and for GCN 1.2 and later GPUs. AMD's Carrizo presentation listed this under the Voltage Adaptive Operation moniker, with a nebulous 5-10% power savings mentioned. AMD touted this as a new feature for multiple GPU generations, though there were claims that at least some of them did not enable a significant number of their power management features outside of their launch slides.
It seems as if there's more effort in taking it out for any future microarchitectures.
At least points 1 and 3 seem like generally measured and accurate descriptions of certain aspects of low and high level API behaviors, while the others seem rather straw-man or not well-grounded.
It would depend on what counts as the target RT workload, what aspects are supported in hardware, and what form that support takes. The longtime rough rule of thumb to follow from hardwired specific-purpose, to specialized, to general has been something like moving along a continuum with a 10x increase in complexity and overhead for those three points.
If there's no highly specific algorithm, the most area and power efficient hardwired scheme would likely be too inflexible, but the other end of the spectrum is hardware that needs significantly more area and infrastructure to be used generally.
General-purpose hardware also tends to need the surrounding infrastructure to scale up to allow its being used more generally, which can lead to knock-on effects where other portions of the chip become more heavily burdened or need to grow outside of the generalized unit.
