Interesting article on PS3

That's one long and well put-together post there. I can feel my brain melting trying to absorb it all right now... :oops: :D He certainly seems to be describing the "as optimal as optimal can be" situation, though.
 
Yeah i managed to just about read through it, took me a while though, having said that I didn't really understand some of the finer points, I thought if anyone would get something out of it though, you guys would. Some of the stuff he is talking about sound pretty good, but I have learned to take a lot of what Sony says pre hardware release with a pinch of salt - Emotion Engine anyone? Other bits just sound too much like a flight of fancy though.
 
I just showed that to a ex Rockstar Ps2 programmer and he thought parts of that article sounded like he was trolling. In two sections he singled out the 1 billion polygons persecond figure along with the fact an ex Naughty dog programmer was posting this on a Xbox forum as some interesting clues.
 
Sorry, I did a search for naughty dog, thought that might turn it up if it was there but nevermind.

Edit: QRoach: As far as I know, its not the coder himself posting, but someone who found the article, whether or not its the guy posing as a third person is open to debate.
 
Quincy said:
I just showed that to a ex Rockstar Ps2 programmer and he thought parts of that article sounded like he was trolling. In two sections he singled out the 1 billion polygons persecond figure along with the fact an ex Naughty dog programmer was posting this on a Xbox forum as some interesting clues.
The text doesn't originate from a forum post afaik, but apparently from author's "PS3" site which was subsequently removed.

Anyway, what's so bad about the 1bilion poly number? The guy is writting from the assumption that PS3 will have a 1TFlop chip, which would give you a nice fat 1000Flops per polygon if you draw 1bilion of them per second.
And you only need around 40Flops to do a basic transform with perspective texture.

If you accept a Teraflop chip, then his peak poly number is actually quite conservative.
 
If you're drawing 1B polys per second, the average size of each poly isn't going to be very big, a couple pixels at most even at fairly high resolutions. 1000 flops for a couple pixels should be "enough", don't you think? :)
 
Megadrive1988 said:
I read this article last year. I think its from April.

1st April?
erst111.gif
 
...

It is my understanding is that the actual CELL doesn't look like the SCEI proposal described in the patent application, based on James Kahle's comments.

I am expecting around 8 stripped down 32-bit Power4 cores packed into one chip.
 
Re: ...

Deadmeat said:
It is my understanding is that the actual CELL doesn't look like the SCEI proposal described in the patent application, based on James Kahle's comments.

I am expecting around 8 stripped down 32-bit Power4 cores packed into one chip.

Your understanding of his comments is wrong: look at actual patents filed by him and the other 4 connected with the STI CELL project from within IBM ( hint: do a search on this forum as I have posted them already )... you will see how they do not negate Suzuoki's patent, but connect to it very well.

I will post them again soon.
 
Re: ...

Deadmeat said:
I am expecting around 8 stripped down 32-bit Power4 cores packed into one chip.

I'm curious... Do you have any ideas in particular to explain why Sony would go from a 64-bit dual-issue/128-bit single-issue CPU to a 32-bit CPU? Other than you'd perhaps prefer if it was 32-bit from ideological reasons, I mean.
 
Re: ...

Panajev2001a said:
Deadmeat said:
It is my understanding is that the actual CELL doesn't look like the SCEI proposal described in the patent application, based on James Kahle's comments.

I am expecting around 8 stripped down 32-bit Power4 cores packed into one chip.

Your understanding of his comments is wrong: look ata ctual patents filed by him and the other 4 connected with the STI CELL project from within IBM ( hint: do a search on this forum as I have posted them already )... you will see how they do not negate Suzuoki's patent, but connect to it very well.

*Pulls up lawn chair*

This will be good, I look forward to your responce Deadmeat wrt why the same 5 members of IBM's contact team which basically layed out the Cell architecture with Sony and Toshiba would all be attached to patents which are basically mirror's of the Suzuoki one and are from the timeframe defined by Kahle's Designchain article as STI's defining of the Cell architecture, as well as placing them in Austin, and in agrement with Sony's comments. What a remarkable chain of events that all mysteriously occured, eh?

And what's even funnier is that you once quoted one of the patents which talked about redundant logic for fault tolerance and stated that the 2 PE's in the PS3 will each have 8 APUs and a spare - remember that?!? If I didn't know better, I'd question just what goes on in your head wrt your constantly changing positions.
 
Vince,

"Processor with Redundant Logic" ( James Kahle, chief architect of CELL in IBM )

http://makeashorterlink.com/?M1B322DC6


"Simmetric Multi Processor System" ( James Kahle, look at FIG.2 :) )

http://makeashorterlink.com/?B3D322DC6


"Processor Implementation having unified scalar and SIMD datapath" ( Michael Karl Gschwind, Harm Peter Hofstee, Martin Edward Hopkins... this is basically one of the nicest APU patents together with Kahle's one and what we find about the APUs in Suzuoki's CELL patent ).

http://makeashorterlink.com/?M1F352DC6


"Processing Module for Broadband Networks" ( this is Sony's own Masakazu Suzuoki's CELL patent )

http://makeashorterlink.com/?T1C363DC6
 
nobie said:
I think he was talking about the speed of scan-conversion, not T&L.
No, he is discussing the feasibility of software rendering, which scan-conversion is a part of.
The problem is that writeup is entirely based on assumption that the Suzuoka patent=100% PS3. Personally I think this is offbase on a number of counts, but let's remember it was written nearly a year ago, if not more.

DM said:
It is my understanding is that the actual CELL doesn't look like the SCEI proposal described in the patent application, based on James Kahle's comments.
I am expecting around 8 stripped down 32-bit Power4 cores packed into one chip.
It was also "your understanding and expectation" that XBox2 will be a uniprocessor Intel x86 PC in a box, and you were wrong on every count of that.
Curious though, is your sole aim to post on a forum to express a direct opposing view to whatever topic is being discussed?
Namely, in your original observation of PS3, you were literally saying that APU=VU. Why the sudden change of heart to this new view, conveniently right after you see a writeup that actually agrees with you. You can't stand your statement actually agreeing with someone?
 
Fafalada, even in Suzuoki's patent ( which might or might not describe the GPU of the system [only the Broadband Engine made it public with the Sony/SCE + Toshiba + RAMBUS contract] ), it leaves plenty of space for dedicated silicon where it makes sense ( especially on a possible GPU: Texture sampling and filtering, mip-mapping, etc... ).

I do not think we should view the Broadband Engine and the hypotetical Visualizer as designed for pure 100% software rendering.


What are the parts of the patent you se off base and disagreeing with the other IBM patents I posted or just simply sounding weird to you ? ( you could post here or PM if you want )
 
based on assumption that the Suzuoka patent=100% PS3
He is not the only person that finds the assumption too... presumptuous. For a simple reason that the paper was written to be general, applicable to a wide variety of products(that is, they hope it will be), with a lot of wriggle room for ways of implementation.

Anyway I don't want to spend too much time discussing why or why not (the patent) = (100% PS3). With a very-likely early 2006 release(Japan at least) just 2 years away, details should be surfacing soon. When did devs learn about PS2 details before its launch?
 
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