esram astrophysics *spin-off*

The physicist card was already played by astrograd so now what's left in the deck?

 

And again you completely miss the most important point. Namely that we speak of a flipflop as a clocked device. It will change it's state only on a certain, predetermined clock edge (either rising or falling edge).

Would be a bit OT. But for starters, I would question that tighter packaging of transistors raises their drive current (at least that's how one could interprete your "higher probability of transmission" for the electrons). And while shrinking transistors indeed tends to increase their switching speed, I would prefer to use the more classical explanation of decreased capacitance. Your explanation better covers (a part of) the increased leakage (which is a bad side effect).

Hey! I didn't introduce this "who else is a physicist?" topic. Maybe you didn't notice that my edit was just an answer to astrograd's boasting about his prowess as theoretical physicist and questioning the capability of others here to follow his arguments about quantum mechanics. I was just giving him a hint that this doesn't impress me much. So I'm on your side here.

edit @mods: Nice split and rename!

 

He was just defending me against astrograd because I'm a grade-school drop out. I didn't like this useless alphabet thing.

 

As far as I can tell, a PhD (negative log of hD?) tends to be highly specialised, and generally useless . I don't have any engineering degrees, all of mine are in theoretical sciences. Of course, everything I've done since college has been practical applications, so I suppose I'm an engineer in the end.

As far as I remember, and I'm remembering from way before DDR days, I always had to build my circuit differently if I wanted to read a register out on both rising and falling clock.

 

Why didn't you just invent a hyper-intelligent AI and holographic interface to help walk you through the problem?

 

Some OT (maybe it's now even on topic given the name of the thread?) regarding degrees:

Spoiler

I think one can make a distinction. While the thesis tends to be highly specialized and often useless (not generally, but I would say mine is , edit: I mean the thesis itself, of course not the work I've done), the same does not have to apply to all PhDs. And btw., pHD would be the negative log of the HD concentration (one of my minors was chemistry).

But as you appear not to have a high opinion of PhDs, I'm glad I'm officially not a "philosophiae doctor" in physics. In Germany we like to specify degrees a bit more fine grained, hence we got quite a lot of different doctor degree names for different fields. Philosophers (but it's not that strict: historians, philologists and some social sciences also count) get a Dr. phil. here, for the natural sciences it is usually called Dr. rer. nat. (short for "doctor rerum naturalium"), engineers can get a Dr.-Ing. (a German abbreviation, not a Latin one as obviously the old universities disliked to give that degree to engineers when it was introduced more than hundred years ago ), for law it's called Dr. iur. and so on and so on.

Good to know. Then I was not living in an alternate reality. Because that's how I learned it at some point, too.

 

I don't have anything against PhDs, when I said they were "generally useless", I was using a play on the word "general". I'm just implying that outside of their doctoral domain, they tend to let their knowledge get stale . I've seen it in industry folk too. They tend to get specialized over time. I purposefully change what I'm working on every few years so I don't get like that, but then I've always been a generalist.

Always nice to be in the company of geeks who get obscure chemistry jokes though.

 

For that generalist thing it's also helpful to spend some time doing something else than one is supposed to (hope my boss doesn't read this).

 

Can't help but think that pic is what some expect next motion controls to be like....

 

Love yah' all people. The title of this thread is awesome. I am sorry I can't write a meaningful reply but it's so late here and I gotta work tomorrow.

p.s. All this technical jive sounds like hearing a term like Phase Coppers to me. I can understand what it means but I never cease to wonder how it works exactly. Gipsel and 3dilettante are very very very very very very very knowledgeable on the matter, so they can help astrograd to shed some light on the subject. I also see that bkillian is posting here too, but I gotta go, so yeah. GN

 

All I can say is that I have a huge appreciate for anyone that is highly educated in physics or pure math. It's a path I wish I'd taken when I was in school.

 

I know this, but it doesn't apply to the problem at hand. You have to consider the largest effects first.

I thought it is common (to B3Ders) knowledge? You probably have also not heard that a rough scaling law for the dynamic power consumption is often given as P~C*U²*f? Maybe you want to look up how much energy is needed to charge/discharge a capacity C to a voltage U f times a second and ask yourself how the power consumption can be reduced with a shrink?

No, I don't know that. I know that almost all integrated circuits use CMOS transistors which are field effect transistors. Ideally, the electric field of the voltage applied to the gate electrode controls the state of the transistor without any charges tunneling. The tunneling from the gate into the channel is unwanted leakage caused by the imperfect gate isolation. And there is a reason why the gate (and isolation) materials got changed when the industry arrived at smaller processes...

 

To be fair,

I worked on devices where we had a certain bus controller and storage device that was capable of operating at a variety of clocks, voltages, and both SDR and DDR modes. This was all configurable through software by setting some hardware registers.

We ended up picking which clock and mode we shipped in based on thermals, power consumption, and stability.

So it is (very slightly) theoretically possible MS built a controller that could run in a variety of transfer modes, built an SRAM array that also supported a variety of modes, simulated how it could operate, and settled on an initial clock rate and data mode.

Then after they got the chip fabbed, real tests on the chip figured out what modes and clock rates it could actually safely operate in, and maybe they got lucky.

By a lot.

Yeah.

Not saying this is what happened with Xbox One, but it is probably wrong to say this kind of thing is *impossible*. Very unlikely yes, but not impossible.

 

This is an interesting debate because it's based on science and facts. There's no room for interpretation when it comes to how transistors and clocks work, which means suitably educated folk should reach consensus. Either it's possible, given the nature of small integrated circuits, for MS to have found an opportunity to read twice on the clocks as astrograd says, or its not as Gipsel says. I would like to see, just for once in this life, an argument where two different viewpoints in discussion resolve to one as someone comes to see how they were wrong - either Gipsel saying, "oh, I didn't know that. In that case you may be right," or astrograd saying, "I've been reading papers on this for five years, but you're saying it doesn't really work that way. Wow, okay, I guess I was wrong then," or something. It'd also be nice for the topic if we could come away with some sort of explanation for the eSRAM BW change, which, with two diametrical opposed voices and no frame of reference of my own, remains a question mark to me.

That said, I have nothing to contribute to this thread and can only hope Gipsel and astrograd and whoever else is suitably educated and interested go the whole hog and discuss to a worthwhile conclusion. I do respect astrograd for not backing down earlier on and pushing the discussion in this direction.

 

I think one of the bigger problems people have with the reasoning is it relies on you having a memory controller that has a DDR for 15/16 clocks and a SDR for 16/16th clock

 

I would claim that in your example it only worked, because the possibility of both SDR and DDR modes where considered in the design. Astrograd is basically claiming that one could switch to "double pumping" on any interface and one doesn't have to consider it in the design, that it is just a matter of timing margins (possible clocks are a matter of timing margins, such mode changes have to be taken care of in the design). Of course you can build something capable of multiple modes. But then you know of this capability before the silicon comes back from the fab, simply because it was designed that way.


@astrograd:
I still don't get how the Casimir effect and the restricted spectrum of vacuum fluctuations between two metallic plates have any closer relevance to the timings of a CMOS circuit.
And nice dodge on the transistor state change. But it is still done in the first place by applying a voltage to the gate. You overrate the tunneling in my opinion. The current through the channel is not tunneling if you switch the transistor to create a conductive channel. And a thermal excitation isn't tunneling neither.

And look how a planar transistor looks like and now imagine a node shrink so the consumed area halves (and yes, I know it isn't done exactly this way anymore). Things change a bit with FinFETs, but otherwise the gate electrode area usually goes down with a shrink (which is a significant factor for the severe subthreshold leakage problems we got, not so much the area but the length).
And btw., that scaling law can't be off by a factor of 2. It only gives the proportionality of changes. You can rescale with any constant factor that pleases you. That's the reason you haven't seen an "=" sign in it (∝, as commonly used today in English for proportionality is usually hard to find on a keyboard, the German version "~" much easier, and it also designates similarity in geometry, which is actually quite close to mean being proportional [same shape, scaled in size, can be rotated or flipped], which is why one may find it occasionally also in English texts with this meaning; just to give you the reason for my choice). As I explicitly mentioned a scaling law, I hoped it would be understandable. You can't use it to directly calculate the power consumption anyway without adding a few other terms (especially with todays small feature sizes, some years ago it was a better aproximation). But it still catches the main effect and was just meant to illustrate the importance of the capacitance.

On another note, maybe TFETs become useful for some low power SRAM (and are relying on band to band tunneling for carrier injection), but these are simply not used in all the prevalent CMOS devices.

I think it doesn't make sense to dig deeper into that stuff as it has not much to do with the original point made. Agreed?