@astrograd:
I still don't get how the Casimir effect and the restricted spectrum of vacuum fluctuations between two metallic plates have any closer relevance to the timings of a CMOS circuit.
They don't. I never claimed they did.
Do I need to explain what quantum tunneling is again? Yes, it involves a potential barrier. That's what gets tunneled through. And yes it involves the electrons' energy levels, which are adjusted via inducing electric fields in the dielectric to 'trap' the conduction electrons and kill their mobility. Tunneling rates are dependent on system parameters (obviously), including the voltage across the material. I'm astonished that you assert I 'dodged' anything given the explanation I offered.And nice dodge on the transistor state change. But it is still done in the first place by applying a voltage to the gate.
Tunneling is the physical basis of the Kronig-Penney model from which semiconductor physics arises from. Periodic crystal lattice potentials with exponential Bloch functions are what gives you the energy bands in the first place. The Bloch functions exhibit tunneling just like any other wave function in a lattice would.You overrate the tunneling in my opinion. The current through the channel is not tunneling if you switch the transistor to create a conductive channel. And a thermal excitation isn't tunneling neither.
I've noted the classical equation already for capacitance. We can surely agree that it's correct and yes, it's proportional to area and inversely proportional to planar separation. I was simply asking for clarification as you asserted something in a vague fashion that isn't necessarily true if someone interprets your meaning as shrinking one dimension when you meant another.And look how a planar transistor looks like and now imagine a node shrink so the consumed area halves (and yes, I know it isn't done exactly this way anymore).
Fair enough. I didn't notice that word there the first time. I was obviously referring to the actual formula. I see now that you did say it was for scaling, so that's fine. You may ignore my nitpick. But don't presume to assert what I am or am not aware of please.And btw., that scaling law can't be off by a factor of 2.
You're talking to someone who researches quantum gravity for a living. You don't need to explain scaling relationships to me. You can afford to be condescending when you actually make a point premised on nuances I hadn't considered.It only gives the proportionality of changes. You can rescale with any constant factor that pleases you. That's the reason you haven't seen an "=" sign in it (∝, as commonly used today in English for proportionality is usually hard to find on a keyboard, the German version "~" much easier, and it also designates similarity in geometry, which is actually quite close to mean being proportional [same shape, scaled in size, can be rotated or flipped], which is why one may find it occasionally also in English texts with this meaning; just to give you the reason for my choice). As I explicitly mentioned a scaling law, I hoped it would be understandable. You can't use it to directly calculate the power consumption anyway without adding a few other terms (especially with todays small feature sizes, some years ago it was a better aproximation). But it still catches the main effect and was just meant to illustrate the importance of the capacitance.
That doesn't mean tunneling isn't the physical mechanism for MOSFETS used in CMOS designs. When electrons move through the semiconducting solid they tunnel through the potential barriers centered on the periodic lattice point nuclei. That's how conduction works physically. FET's kill that by lowering the kinetic energies of the electrons by entrapment via Coulomb attraction, but make no mistake...the reason they are 'trapped' and immobilized is because of the low KE not being high enough to effectively tunnel across lattice potentials. The exact same physical effect is at play there governing the conductance.On another note, maybe TFETs become useful for some low power SRAM (and are relying on band to band tunneling for carrier injection), but these are simply not used in all the prevalent CMOS devices.
My only point on tunneling in the first place was that as you shrink your system it becomes more important for determining the time it takes for states to change. You seem to prefer arguing about how big a difference this makes, but neither of us have the details to actually do the calculations without knowing how things are doped, what materials are being used for the semiconductors, what voltages are put in place, etc.I think it doesn't make sense to dig deeper into that stuff as it has not much to do with the original point made. Agreed?
I was never claiming that tunneling was the most apparent thing that would affect timings as you shrunk the eSRAM array. I was trying to speak to what could have those effects while alluding engineers and believe, quantum mechanical effects almost always allude engineers, even electrical engineers working in large labs at AMD et al. In any case, we can drop that issue if you like.
As someone else noted from their own experience, it seems that my conjecture is absolutely possible for real world manufacturing scenarios and my conjecture (obviously) does fit what I was told (which was vague but not worthlessly so) and it is in line with what MS apparently told devs. I find it hard to believe that MS told devs something was achievable in real world usage (133GB/s) if they didn't test it out first to make sure. The picture you painted on how DF got the info they did just sounds totally implausible and it doesn't match what little I was told on the subject personally.