No, you can't get it to work at all. We are talking about clocked designs, aren't we? The reaction to the clock edges are predetermined. You can't change an SDR design to a DDR one without a significant redesign.
esram astrophysics *spin-off*
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Never give up. Never surrender!
Are you sure you wanna give up on 2 gpus? How about pile driver based cpu, we don't know that it is not!! I mean if you are positing that they are making smaller transistors to double pump that would mean a smaller process to fabricate these smaller transistors , meaning 22nm or something like that. If 22nm is in play who knows what's in that APU!!
Simple logic. The actual physical implementation of the design stops you from doing it. If it is designed for SDR operation, it is doing something on each rising clock edge. How should the transistors know that they have to react on both, the rising and the falling clock edge? That's nothing you can patch in easily just by applying a few other timings. One has to design for that, explicitly. Or has anybody ever succeeded to run a PC-133 SDRAM-Module as DDR-133?
Just to be clear since we may be losing track of it in the back and forth, DDR isn't synonymous with double pumping the RAM. DDR is designed around exploiting the double pumping techniques ppl tried using on SDR RAM historically, but the two aren't interchangeable. One is a technique for gaining higher bandwidth and the other is a classification standard for RAM that was built ground up to harness that technique's benefits. I'm sure you realize this, but I don't want it leading to confusion.
What I heard was the eSRAM was double pumped on 7/8 of the cycles. Your posts come off as if you are conflating the two and deciding that you can't possibly double pump something designed for SDR. But that's not necessarily true. Ppl tried and failed since they couldn't get the timings narrow enough to make it work. But as I mentioned, those timings are based on the physical properties that are related to manufacturing challenges that have since seen significant improvement, and as such a refinement on those manufacturing procedures may well result in an output chip that just happens to be tight enough to get some of the cycles to do read/writes within a single cycle.
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I never said there were ever 2 GPUs, nor piledriver based anything.
And I didn't say anything about 22nm. I said that making the transistors small you can make them change state faster, which is true. I can show you the quantum mechanics behind that assertion if you like.
Is there any point to have a DDR clocking for something that doesn't even go through an external PHY? I thought the move from SDR to DDR memory clocking was merely solving a PHY issue.
Maybe they used quantum mechanics to make the transistor smaller, on a 28nm process... but you can ignore any science assertion where "quantum mechanics" is the most complicated phrase in it.
http://xkcd.com/1240/
Maybe they used quantum mechanics to make the transistor smaller, on a 28nm process... but you can ignore any science assertion where "quantum mechanics" is the most complicated phrase in it.
http://xkcd.com/1240/
You can explain it then. Please proceed. Sharing is caring.I'm a theoretical physicist. I can assure you I'm not misusing the subject matter.
You can explain it then. Please proceed. Sharing is caring.
How much math background do you have? Specifically with 2nd order differential equations...? Basic wave mechanics (understanding Dirichlet conditions is sufficient for this application)? I presume you know calculus?
If you have this stuff down pat, then it's a straight forward application of quantum tunneling. Take a particle in a potential well, write out the solutions to the Schrodinger Eq. in the regions to the left/right of the well boundaries (they will be exponential decay/increase in these regions). You match the solutions at the boundaries, apply Von Neumann conditions at the boundaries (to keep the solutions smooth), and then after playing with the linear algebra a bit you can derive the probabilities for the reflected/transmitted portions of your solutions. The transmitted part, you will find, is a decaying exponential with its characteristic decay length inversely proportional to the thickness of the boundary walls. When you move transistors together, you pinch those walls and thus the characteristic decay length grows, meaning your wave solution decays less before reaching the other side of the wall.
The result is your solution decays less by the time it 'tunnels' through the wall. If that solution is describing an electron and your potential well is the junctions of a transistor, then what your transmitted solution tells you is the probability amplitude of finding your electron has moved from one side of the boundary to the other, i.e. you've got the probability of a current arising. Tighter packing of transistors means thinner boundaries, which in turn means less decay and higher probability of transmission, hence quicker change of state from being read (current) to write (voltage).
Happy? Do you need me to walk you through the math step by step?
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Let's be clear: you did not 'hear this'. You made this up out of whole cloth. It's in your post history.
I'm a theoretical physicist. I can assure you I'm not misusing the subject matter.
Ahhh, good. Because I actually have a lot of training on theoretical and applied physics. I used to operate nuclear reactors and its sort of required. My good buddy who is visiting (and sitting next to me right now) also went through the same courses and he has training above and beyond mine in electronics and their theory.
Please, go right ahead. This should be wondrous.
No, I did hear it directly from a source of mine actually. In fact, there are ppl here who can prove as much (and one has brought it up before in fact).
Ahhh, good. Because I actually have a lot of training on theoretical and applied physics. I used to operate nuclear reactors and its sort of required. My good buddy who is visiting (and sitting next to me right now) also went through the same courses and he has training above and beyond mine in electronics and their theory.
Please, go right ahead. This should be wondrous.
Enjoy. You might refer to the Gamow model for nuclear decay as a good analogy here in fact. Just replace Gamow's decaying potential with a flat box top for the 'walls' instead.
This happened before the reveal. Also, to be clear, I'm not talking about getting down below any particular threshold. Simply stating that it's not uncommon to adjust the physical properties during manufacturing phases that are relevant to opening the windows for double pumping on a by-design SDR setup.
DING DING DING!
Yikes, I see physics from 9 decades ago is a bit too 'fresh' for some of you guys. Btw, were you in the Navy? Just curious if you 'learned' physics from one of their knock off NUPOC 'instructors' since I know they recruit those types. If ya wanna chat/learn more about physics you can PM I suppose. Needless to say, quantum tunneling is a very important part of how quickly a transistor can change states from current input to voltage output.
I'm far from confused. I just used an example I thought it would be easy to grasp for everyone. According to your reasoning it should have been possible to use some SDR-SDRAM chips und hook them up to some interface using DDR signaling.
This is most definitely true. You have some pipelining going on when accesing the eSRAM. If you shift your signals through that pipeline once a clock cycle or twice is not just a matter of some timing margins. The circuit have to be specifically designed for it to work that way. It's a really basic fact. Any timing margin in this world won't change the behaviour of a simple clocked flip flop for instance. You need to design any DDR capability into your circuits, otherwise in the best case they just ignore anything on the falling clock edge or more likely produce erratic behaviour.
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Your quantum mechanics reasoning is largely irrelevant to the problem (even to the point tht you come to wrong conclusions). Says someone with an actual PhD in physics (me). But okay, I know enough theoreticians (and also a few experimentalists) without a clue outside of their field.
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Silent_Buddha
Legend
Umm, take away those DMA's and watch every single I/O request from the OS bring the OS to a screeching halt. Have fun using HDDs without DMA enabled as an example. Either you'll have frequent OS stalls or you'll have frequent HDD stalls when reading/writing to HDD depending on which one takes precedence at any given moment.
DMA's are essential to fast, efficient operation when data transfers are involved. Hence why both Xbox One and PS4 have them. That does not however mean that the DME's are equivalent to whatever type of DMA is used in the PS4. Nor does it mean they are necessarily vastly different.
Regards,
SB
That's fine. I was noting it because I was starting to wade into the laxy usage of the terminology with ya and it seems to be the basis of the arguments revolving around 'you have to design for this, ya don't magically discover it'. That line of argument seems premised on viewing the eSRAM boost as a complete swap from one design to something else when that isn't what was ever being claimed, so I wanted to get that cleared up for everyone.
No. The DDR interface is designed from the ground up to operate with certain inputs to carefully exploit the timings (for instance, some of the timings present in SDR are erased entirely in DDR).
Double pumping is simply a matter of timings. The special pipelining you are talking about is the basis for the DDR design in the first place. That was the 'ground up' design I mentioned earlier. It's not required for double pumping in theory, it's just a vastly more efficient and reliable way to get it.
The circuit has to be able to double pump, but again, the physical properties that determine if it can be double pumped are in flux alongside the manufacturing processes and testing. The way you govern the timings your circuit allows is purely by varying these physical parameters.
The physical characteristics of a flip flop circuit WILL change state under certain conditions. Not sure where you got this idea that the physical properties don't govern that timing. The flip flop circuit, for instance, changes state based on the resistor values it uses for the base-bias in each half. Those resistor values are temperature dependent. The charge decay on the capacitors (and thus the current flow parameters) are sensitive to the resistance. The timing of the back/forth flip flopping is dependent on the circuit's time constant (the product of resistance and capacitance), and hence it too is temperature dependent. That doesn't even account for the thermal excitations of the electrons/holes in the transistor junctions used in such a circuit either, which also affects how fast the state can change in that piece of the circuit.
We aren't talking about DDR. You're conflating again.
They aren't the wrong conclusions. Feel free to "correct" them if you see fit.
Dude, degrees in physics are a dime a dozen.. I have one too, although mine is also in electronics. Don't use your degree as a bludgeon to silence dissent, revel in it, not matter how far fetched and incorrect it may be..
Silent_Buddha
Legend
Dude, degrees in physics are a dime a dozen.. I have one too, although mine is also in electronics. Don't use your degree as a bludgeon to silence dissent, revel in it, not matter how far fetched and incorrect it may be..
Damnit, I feel left out that I don't have a physics degree, although I did study some advanced physics in college.
Regards,
SB
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