Does Cell Have Any Other Advantages Over XCPU Other Than FLOPS?

Edge said:
Well each SPE is dual pipelined, so using your logic, each SPE can support dual threads. I don't consider that dual threading, and your example is incorrect also, as dual threading has to consider being able to run dual threads on the ALU, which it cannot, as one thread running, has to stop the other thread. Dual threading on the PPE's is only for faster context switches, and thus only supports 10 to 20 percent increase at most.
I'm not sure where you are getting this information from.

Dual pipelining is not the same as dual threads is not the same as dual register sets. You seem to understand that all SMT is is dual sets of registers to negate performances of context switching between two threads. That is absolutely incorrect.

Dual threading does not mean dual execution!!!
In this case, it does; provided that each thread has access to a component of the chip not in use.

Your example also, would be very limited to an algorithm, supporting both DIFFERENT types of execution, which I would think would be a RARE occurance.
Absolutely not, especially given the fixed platform nature of game consoles. One thread doing procedural geometry creation, the other doing AI. Both threads typically mind their own business in different sections of the CPU.
 
xbdestroya said:
Asher no offense, but I just don't see Barry Minor flat-out lying about this. Maybe there's some shade of grey thing going on, but I think you're going to have to offer more up than your resume, since Barry's is more impressive. Now that you've given us the 'simple' way of debunking it, I think we're ready for the next step up in difficulty.
Sorry, I should have quoted more carefully. There is an experimental feature in development to compile to register ranges, but this does not mean we can say Cell can support "64 threads". That, is nonsense.
 
I didn't think integer CPU performance was the bottleneck in most modern games. Why do we keep coming back to this general purpose CPU issue.
I feel like dwelling on integer performance is a moot point unless your goal is to nitpick flaws in the architecture.

Isn't the idea behind Cell for the PPE to run basic game code while forking off computational intensive tasks to the SPE's to operate on in parallel. Sounds like a reasonable application for a stream processor to me.
 
DeanoC said:
AFAIK xlc (IBM) is the experimental compiler (thats always been that way), so you might get an insight into some possible strategies from that, but currently I've seen nothing on the same league as MS research stuff.

IBM are trying mad ideas in a desperate attempt to make Cell easy but IMHO they really seem to be missing the point... and MS are actually trying to solve the issue the right way (accept that there is no magic bullet, so change the language to help coder and compiler).

I have the even less faith in auto-parellisation than auto-vectorisation (and I have NO faith in auto-vectorisation).
The major focus of xlc/xlC/xlf (they all share the same backend) development isn't on the SPEs right now. There are some very interesting (and patent-pending) optimizations coming soon in an upcoming version of the compilers, and a couple of these are applicable to SPEs.

IBM makes very little money from Cell/Xenon compared to their other bread and butter products, the compiler development and research teams have their main focuses elsewhere. I wouldn't hold my breath for anything massively different for xlc and SPEs. MS has more motivation here (and more money to throw this way) into compiler and development research. IBM just designed the chips. =)
 
Edge said:
What ever, my who point of using the term secondary thread, was just to point out, that dual registers to support dual threading, does not mean dual execution. Dual threading supports at most 10 to 20 percent performance advantage.
Again, you fundamentally misunderstand what multithreading is. It is not just duplicating the register set. The initial implementations many years ago were like that, modern SMT lets multiple threads compete (in real-time) for resources on the same chip.
 
Asher said:
They can, but it's a bit like doing a "cone challenge" with a semi-truck. It works, you just gotta go real slow.
I'm not sure I'd agree that always holds. I've seen VU with it's almost non-existant branching and integer support outperform EE core in decision heavy code, simple courtesy of local memory and zero-penalty branching.
Granted SPE hasn't got the latter :/ but on the flipside it actually has an ISA with some real integer functionality.

One thread doing procedural geometry creation, the other doing AI. Both threads typically mind their own business in different sections of the CPU.
Ah, those would be the threads running exclusively inside Geometry and AI execution pipelines, right? :p
 
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Fafalada said:
I'm curious, what kind of new language development is MS working on?

Don't know what MS research is doing, but what you need to do to a language to make it parallel friendly isn't exactly rocket science.

First thing you need to do is make mutable variables extremly RARE, ideally none existent.
After that you can help the compiler out by making all scope explicit give it enough information that it can establish all possible codepaths.
Loose anything in the language semantics that dictates order of potentially parallel operations (make sequential operations explicit).
Add some sort of native concept for streams with sliding windows.
Add Vectors as a native type (The compiler can then do all the nice stuff it does with other built in types).
Add Hints.

Most functional languages meet the first two criteria. The third is just a language design decision, and the last three aren't terribly hard to come up with solutions for. With all that the compiler has enough information to have a shot at generating parallel code, and it's very likely to make extremly poor decisions doing it.

I think a better model is to implement the above minus point 3, and use it to generate jobs that an explicitly parallel model can run. Building a language like the above makes it much harder to screw yourself with unintentional side effects.

Of course even with all that (and what's described is a language with very little in common with C or C++) you still have to solve the scheduling problem and given the instruction latencies of these processors and the in order designs that's far from a given.
 
Asher said:
IBM makes very little money from Cell/Xenon compared to their other bread and butter products, the compiler development and research teams have their main focuses elsewhere.

If we're talking about their semiconductor division, then IBM doesn't make any money period. ;) I think they're hoping to possibly change that with Cell and the console chip orders they have. Whatever the case, Cell seems to be getting some decent support from within IBM.

On the side though, what differentiates 'short-integer' from integer performance - or more importantly what tasks would generally utilize the former? I ask because Mercury Systems, the only notable third party onboard Cell right now, touts it's upcoming Cell product's superior short-integer performance.

For reference: Blade server
 
xbdestroya said:
On the side though, what differentiates 'short-integer' from integer performance
Maybe by short they mean the C/C++ name for 16bit integers.
SPE integer ISA doesn't having explicit instructions for multiply/multiply-add on 32bit operands.
 
DeanoC said:
AFAIK xlc (IBM) is the experimental compiler (thats always been that way), so you might get an insight into some possible strategies from that, but currently I've seen nothing on the same league as MS research stuff.

IBM are trying mad ideas in a desperate attempt to make Cell easy but IMHO they really seem to be missing the point... and MS are actually trying to solve the issue the right way (accept that there is no magic bullet, so change the language to help coder and compiler).

I have the even less faith in auto-parellisation than auto-vectorisation (and I have NO faith in auto-vectorisation).

So basically PlayStation 3 development kits are crap compared to Xbox 360's development kits? :???:
 
Fafalada said:
I would take a changed hardware too to help me :p
Ok Ok I promise I'll stop. But I'm curious, what kind of new language development is MS working on?
MS have done work on a C++ varient called Concur, that they are promoting as the basis of the C++ ISO200x standard. The basic idea is a ERP said pretty simple, add a few key words to C++ that indicate parallism... I have no idea how good it works but the fact they're at the point of introducing a new varient on C++ is IMHO good. I'm strongly in the 'its got to be C++ in new clothes' school of language design.
 
dodo3 said:
So basically PlayStation 3 development kits are crap compared to Xbox 360's development kits? :???:
Don't ask me... I haven't use a X360 dev kit since the original Alpha boxes...

Breaking things into threads is quite hard but that applies equally to Xenon as much as PS3.

One thing MS have is the Visual C++ team, we use their IDE (via SNSYS integration) but I do miss the VC debugger and compiler. But the version of GCC we use is a hell of better than the ol' PS2 one, so I can' t complain too much.

Overall PS3 development has probably been easier than I originally expected...
 
A good solid CSP library being part of the standard (similar to how STL became part of the standard) could help a lot as well.

Cheers
Gubbi
 
DeanoC said:
Don't ask me... I haven't use a X360 dev kit since the original Alpha boxes...

Breaking things into threads is quite hard but that applies equally to Xenon as much as PS3.

One thing MS have is the Visual C++ team, we use their IDE (via SNSYS integration) but I do miss the VC debugger and compiler. But the version of GCC we use is a hell of better than the ol' PS2 one, so I can' t complain too much.

Overall PS3 development has probably been easier than I originally expected...

I see. By the way, I don't know if you're allowed to answer this or not, but you will recieve the final development kits (PS3) in early/late December, correct? Has Sony said or implied these final development kits to include a HDD?

By the way, thank you for your quick reply. ;)
 
dodo3 said:
I see. By the way, I don't know if you're allowed to answer this or not, but you will recieve the final development kits (PS3) in early/late December, correct? Has Sony said or implied these final development kits to include a HDD?

I'm pretty sure they announced it as such at the Playstation Meeting in July. But then, I'd think all dev kits would have to have a HDD pretty much. It wouldn't be a reflection on whether the retail unit will have a standard HDD or not, though, if that's what you're wondering ;)
 
I don't know how to edit my posts, but I have one more question (sorry if these are irrelevant to the topic) but would you have rathered programmed for the Xbox 360 rather than the PlayStation 3?

I know my questions are completely off-topic but answers would be appreciated. :p I will no longer bother you. :)
 
Titanio said:
I'm pretty sure they announced it as such at the Playstation Meeting in July. But then, I'd think all dev kits would have to have a HDD pretty much. It wouldn't be a reflection on whether the retail unit will have a standard HDD or not, though, if that's what you're wondering ;)

Yes, that was exactly what I wondering. :)

It's too bad though, I'm kind of hoping the PlayStation 3 will have a similar system to Microsoft's, having two SKUs, one having a standard HDD and the other not. Oh well, I can always go to bed and dream. :D
 
dodo3 said:
It's too bad though, I'm kind of hoping the PlayStation 3 will have a similar system to Microsoft's, having two SKUs, one having a standard HDD and the other not. Oh well, I can always go to bed and dream. :D

Just having the peripheral there will effectively mean the same thing. There's no standard HDD on X360, the simple existance of the core pack ensures that. The only difference with having a SKU with a HDD versus one SKU without and a HDD peripheral is that the former may drive greater penetration of HDDs assuming a steady high ratio of HDD-SKUs to non-HDD-SKUs, although I suppose that'd depend on a variety of factors.

Anyway, this is a bit OT methinks.
 
Titanio said:
Just having the peripheral there will effectively mean the same thing. There's no standard HDD on X360, the simple existance of the core pack ensures that. The only difference with having a SKU with a HDD versus one SKU without and a HDD peripheral is that the former may drive greater penetration of HDDs assuming a steady high ratio of HDD-SKUs to non-HDD-SKUs, although I suppose that'd depend on a variety of factors.

Anyway, this is a bit OT methinks.

Yes I agree, this is quite a bit off-topic, like I previously stated and apologies!

I'm mainly concerned of how much easier or difficult it is when programming for the Cell when compared to the Xenon. Ultimately, I hope this won't effect the quality of games if the Cell really is that much more difficult to program for.
 
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