I suppose in that case the reason for a fixed split in the XSX (which MS have said is 10 GB for the GPU), could simply be because of the arrangement of 1 and 2 GB chips across different parts of the bus?
The 10 GB is GPU optimized, but is not exclusive to the GPU. The 10 GB would be the range of addresses that can be equally strided over all the channels, with the remaining space being an extra 1GB on only some of the chips, which Microsoft seems to have decided to handle a little differently due to the channel disparity.
Thanks. So if you could cap the frequency on the 4700S, do you think that could show whether overaggressive boost was causing some of the frequency drops? It does seem to bounce around a lot under the AVX tests.
Possibly, although the tested unit has a very poor cooler, which makes things even less comparable. The cooler and thermal interface would be something the PS5 has an embarrassment of riches compared to this salvage product.
A catch-all voltage for salvage may also worsen it.
I'm struggling to find any useful search hits on "track count selections" (lots of stuff on synths!). Are there any other terms I could be using to narrow down more info on this stuff?
Wikichip has a discussion about the variations on the TSMC 7nm process, in terms of standard cell libraries.
The number of fins and number of opportunities for routing metal through a cell can be adjusted to emphasize area or performance.
https://en.wikichip.org/wiki/7_nm_lithography_process
However, from elsewhere, it was indicated Zen 2 already went for high density:
https://fuse.wikichip.org/news/3320/7nm-boosted-zen-2-capabilities-but-doubled-the-challenges/
There's also a caveat that AMD doesn't need to always default to standard cells, but a whole FPU is a bigger exception than certain things like custom registers and a few key structures.
One thing that did come up in the review is that there's an apparent drop in FPU ports:
This is one possibility that I mentioned when the die shot came out:
https://forum.beyond3d.com/posts/2193153/
My question as to why they would go through this much trouble for what appears to be limited gains in area remains.
Whether it's truly a full halving of ports isn't clear to me.
A few operations like logical ones are tied to ports, and those weren't halved. Perhaps there was a reduction in register file/bypass ports and reduction in functionality while leaving a few basic functions of stubs of the original 4?
edit: misread the heading and thought it was only FPU testing, the logical ops are likely integer domain
Another question is what else changed with division, since that's only on one port in Zen2, so a port diet alone wouldn't account for the drop there.
Okay, thanks again. Now you mention it, I think I read you commenting on AMD DVFS around the time of Road to PS5.
I've been looking around for some Zen 2 power management stuff, and Google led me to this Abstract. Perhaps other people can make more of it than me.
https://arxiv.org/pdf/2108.00808.pdf
I've only skimmed, and some items are at a higher level than the implementation, but it does mention Zen2 using a model with over a thousand monitors.