Current Generation Hardware Speculation with a Technical Spin [post GDC 2020] [XBSX, PS5]
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Ah I missed it or I forgot, everyone said it would have 1TB since forever so it's hard to remember the signal from the noise.
The signal to noise ratio is about as good as when squirrels at holes in my cable line, so when a tech spliced the line water sprayed out in his face.
Don't worry, you're not going crazy(ier), I had to look again at their official material to make sure it said the size [1 TB SSD] @ https://www.xbox.com/en-US/consoles/xbox-series-x .
* Though now I can't recall with specificity when they had SSD size listed, but it's certainly been updated with new media today.
Megadrive1988
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From the DF article they mentioned a total of only 76 MB SRAM [ https://www.eurogamer.net/articles/digitalfoundry-2020-inside-xbox-series-x-full-specs ]:
There are customisations to the CPU core - specifically for security, power and performance, and with 76MB of SRAM across the entire SoC, it's reasonable to assume that the gigantic L3 cache found in desktop Zen 2 chips has been somewhat reduced. The exact same Series X processor is used in the Project Scarlett cloud servers that'll replace the Xbox One S-based xCloud models currenly being used. For this purpose, AMD built in EEC error correction for GDDR6 with no performance penalty (there is actually no such thing as EEC-compatible G6, so AMD and Microsoft are rolling their own solution), while virtualisation features are also included.
Megadrive1988
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So 76 MB SRAM across the entire SoC would be all the L1, L2 and L3 cache together, including what the RDNA2 GPU has.
DavidGraham
Veteran
Why would it be? Ryzen 3700X has 38MB (L2+L3) of cache, the GPU maybe has 10MB, that leaves plenty enough for other uses.
Error correction is irrelevant to memory technology or PHY. It's a logic block in the memory controller implementation, and additional memory width the vendor needs to dedicate to it. Saying gddr6 doesnt support ecc is very weird. Ddr4 doesn't specifically support it either, it's not the job of the memory PHY.
That depends on what they're willing to count in the total.
AMD's presentation for Vega 10 stated it had 45 MB of SRAM across the entire chip, which I don't think there's been a full public accounting of.
A 56 CU GPU would have ~14.7 MB just for the register files, ~3.67 MB for LDS, ~2.29 MB for L0, instruction, and scalar caches. Maybe 4MB or more for L2 cache. I'm not certain at this point about the L1, but if this is a 4 shader-array GPU, there's .5 MB for L1.
There could be other caches like the parameter cache, which was 1 MB for Scorpio and might be higher for the next gen.
All these known entities push the buffer totals to a similar amount as the 38 MB figure, so the question is how much of the "other" that wasn't detailed for Vega is in the total for Arden.
The standards can outline a fair amount of details surrounding the DIMM and ECC scheme adopted, which the industry would be unusually consistent in implementing in the absence of a standard. Wouldn't JEDEC have a provision for this for DDR4 DIMMs?
GDDR is more like HBM in how a single device is the endpoint of a channel or set of channels. For HBM, there was provision in the standard for ECC.
GPUs did initially offer GDDR5 ECC by setting aside capacity and additional memory accesses, though this was a less than complete solution for GDDR5 as that standard didn't protect the address and command buses.
GDDR6 is at least somewhat more protected due to the error detection on those buses, though I'm curious what use case Microsoft has for ECC on a console APU. Is there a more high-end workload that would justify such a scheme, concerns about higher penalties from bit corruption due to memory encryption/compression, or maybe a hinderance for rowhammer attacks?
Cloud based work when not being used to run games.
Silent_Buddha
Legend
That made me think of something from the DF article on the XBSX.
Considering that they started development of the XBSX back in 2016, it must have been a very real possibility of the console being a high wattage machine. Back then, they couldn't have known that AMD would have as much success as they have had in increasing the perf/watt efficiency of their GPU designs as much as they seem to have with RDNA2.
So, they were certainly prepared (bolded part) to have to market a very high wattage machines, but it may turn out that they don't have to.
Regards,
SB
Bodes well for their mid gen refreshes.
I guess it is well short of the fantasy vortex-cooled super arrangement some of us might have first imagined. Curious assembly though, that's easy to take apart and put together. Is that to reduce servicing costs? Or enable home-brew hardware modding for alternate cases, water-cooled overclocking, and hacked-in RAM upgrades?
Man, I wish there was more information about this new "Velocity Architecture", and each of the components therein. I would LOVE to see a proper tech demonstration of how it works and the benefits that result from it. I guess that will come soon enough, but still.. it's all so very interesting.
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