Yep it makes a lot of sense.
But it leaves less bandwidth per ROP and per ALU for XSeX.
You're not factoring in the CPU as a consumer of bandwidth and on the PS5, with it's narrower bus, won't CPU memory accesses "block" the GPU more often?
Yep it makes a lot of sense.
But it leaves less bandwidth per ROP and per ALU for XSeX.
You're not factoring in the CPU as a consumer of bandwidth and on the PS5, with it's narrower bus, won't CPU memory accesses "block" the GPU more often?
You're not factoring in the CPU as a consumer of bandwidth and on the PS5, with it's narrower bus, won't CPU memory accesses "block" the GPU more often?
I don't believe in CPUs at all. Should be used less and less each generation.
The architects of both the PS5 and XBSX went in the exact opposite direction, though.
I think it's more "because they can" approach.
An interesting point. I wonder if the split pool was setup to take advantage of GPGPU or machine learning tasks. So the CPU say normally works on it; but when heavy duty job comes by like ML or GPGPU it can call the GPU to do work on the other memory banks.I think it'll actually be the opposite. Because the CPU in the XSX is likely nearly exclusively using the slower memory (which is 192bits), you'll find that the XSX CPU uses comparatively more overall bandwidth time then the PS5 CPU.
I think it'll actually be the opposite. Because the CPU in the XSX is likely nearly exclusively using the slower memory (which is 192bits), you'll find that the XSX CPU uses comparatively more overall bandwidth time then the PS5 CPU.
An interesting point. I wonder if the split pool was setup to take advantage of GPGPU or machine learning tasks. So the CPU say normally works on it; but when heavy duty job comes by like ML or GPGPU it can call the GPU to do work on the other memory banks.
Though having high bandwidth there would also be helpful to be honest. But it’s likely this will be sufficient
I can understand if you think it's opposite if the approach is "narrow and fast" vs "wide and slow". But I wouldn't say 1.8 GHz is slow for a GPU.
So I would not say "exact opposite" directions. They're both using the same CPU, GPU, RAM as a base before they apply their stylings.
It's spreading those accesses over 6 chips as opposed to the PS5's 8, but then there's 4 chips on XBSX which should see very few accesses from the CPU.
I know very little about memory controllers, I'm really sorry. Someone else here would be able to offer a better opinion.Is it possible to schedule a GDDR6 controller granularly?, or will an entire device time slice it?. If it is, the bandwidth for the leftover banks would be quite slow no? only about 224GB/s.
pretty sure the split pool was setup because they couldn’t afford 20GB at the bandwidth they wanted.
Is this a response to me? I was saying that the PS5 and XBSX went in the exact opposite direction from using less CPU.
Not quite. If it was so you would get 6*32=192bit of bandwidth only.
It accesses all 10 chips when using the first gigabyte. And only the first 6 chips when using the second gigabyte (per chip).
Yes, I think? Threads move too fast.
Oh, so you mean current-gen CPU versus next-gen CPU, like PS4/XboxOne compared to PS5/SeriesX? I thought perhaps you means PS5 vs Series X designs.
I know very little about memory controllers, I'm really sorry. Someone else here would be able to offer a better opinion.
They have a high bandwidth memory pool using 10GB, and a second slower memory pool (still fast honestly) with 6GB. I don't think this is coincidence and we'll learn more about it as time goes on I think.
I largely suspect the aim is to take advantage of async compute.
I mean cutting cost while still allowing for higher speed for a majority of the ram is a pretty large advantage. Especially since there is already OS reserved ram that does not need to be full speed. The difference could be $50 of BOM for the console making the difference vs the PS5.Your not the only one who knows very little about memory controllers , i was asking a question not being sarcastic. I dont think there's many, if any scenario where a mixed density RAM is that advantageous outside of the cost reduction afforded.