Are people normalising prices for inflation?
Cost of advanced chip manufacture
- Thread starter IQandHDR
- Start date
These wafer calculators are very basic. and never represent the reality. For example, I can say, that in midlife term, so 1 year after launch, AD102 yields were above 90%. Because there are many methods of getting yields above what the calculator says like dark silicon, redundant blocks, and salvaged dies for lower SKUs
AD102-300 (RTX 4090) is 87.5% of a full AD120 die. (0.91% on Steam)
AD102-175-KEF-A1 (RTX 4070 Ti Super) is 45.8% (0.52% on Steam)
If that +90% yield include dies that are only 45,8% of a full die that numbers is really not very telling.
But then again, I guess is better to recoup some cost on the AD102-175-KEF-A1 dies, than a "blanket loss".
AD102-175-KEF-A1 (RTX 4070 Ti Super) is 45.8% (0.52% on Steam)
If that +90% yield include dies that are only 45,8% of a full die that numbers is really not very telling.
But then again, I guess is better to recoup some cost on the AD102-175-KEF-A1 dies, than a "blanket loss".
Only a tiny fraction of 4070 Ti supers are AD102. Most are AD103 (specifically AD103-275-A1)
The 4070 Ti Super was released long after the 4090. Steam comparisons don’t make sense. Besides the 4070 Ti super is based on AD103.
Most models are indeed AD103, I think 2 other models are AD102 from I can gather.
my data was before 4070Ti launch. I didn't get an update but an educational guess would put this number above 99% if taking into account salvaged dies used on 4070Ti
+99% die rate sounds rather high when looking at this:
www.viksnewsletter.com
They stop at ~90% success rate, what do you base your numbers on?
How Foundries Calculate Die Yield
Understanding the metric that Intel used to abandon a whole technology node.
www.viksnewsletter.com
They stop at ~90% success rate, what do you base your numbers on?
First D0 is below 0.07 at TSMC mature 5nm class process+99% die rate sounds rather high when looking at this:
How Foundries Calculate Die Yield
Understanding the metric that Intel used to abandon a whole technology node.
They stop at ~90% success rate, what do you base your numbers on?
And most important, a defective die can still be used, thanks to redundant areas, dark silicon and entire blocks (where sits the defect) that can be de-activated when making salvaged SKU.
In fact 99% is nothing special. I've seen 99.7% on a 7nm ARM industrial APU project that included a bit of redundancy.
Whoever made this graph is a total moron
I've seen startups making 7nm silicon with less than 50 million dollars in the bank...
In regards to yields:
wccftech.com
"Ousted" Intel CEO Steps In To Defend The Firm's 18A Process, Says Yield Rate % Isn't The Right Metric To Measure Semiconductor Progress
Intel's former CEO Pat Gelsinger arrived on the scene, defending 18A "yield rate" claims by saying that the team is "doing incredible work".
wccftech.com
I had posted about it in the Intel thread as well
Why does anybody pay attention when any of these "news" outlets mention "yields". What yields? For which parts?
Intel has publicly mentioned that the D0 for 18A is under 0.4, and at that point it was like a year to mass production. For comparison for TSMC, D0 for N5 and N7 was ~0.3-0.35 at 3Q before mass production.
Cross posting from the AMD thread since the discussion is more relevant here @Kaotik
As per presentations at IDEM, CFET's are expected to be introduced from the "A7" node onwards, which should follow "A14" (A16?) and "A10", if we take a 2 year cadence, A10 should be in the H2 2028 timeframe and then A7 in the H2 2030 timeframe at the earliest -
The interesting bit is that CFET's could bring a 1.5-2X scaling in SRAM density -
el etro
Newcomer
Cross posting from the AMD thread since the discussion is more relevant here @Kaotik
As per presentations at IDEM, CFET's are expected to be introduced from the "A7" node onwards, which should follow "A14" (A16?) and "A10", if we take a 2 year cadence, A10 should be in the H2 2028 timeframe and then A7 in the H2 2030 timeframe at the earliest -
The interesting bit is that CFET's could bring a 1.5-2X scaling in SRAM density -
This post is gold.
Similar threads
