"..combines four Radeon 8500...based on the 9700..this

1. Split up all the triangles in the scene, so that each video card accepts one quarter of the triangles. These triangles are rendered to a single frame and z-buffer on each chip.


This doesn't work because transparencies generally do not render Z, so you can't recombine the seperate scenes and have the transparencies correctly sorted.

It will most likely either work in tiles or scanline interleaved (ala 3DFX).
 
PCI-X 2.0 266/533 will double/qudr. but it's still in draft phase.

Lets stick with "plain old" PCI-x. ;)

so, my question is same:

Do you think is that enough for this card?

Yes, I do think it's enough. Boards that have 64 bit PCI, they usually have TWO seperate PCI buses. One IIRC runs at 33MHz and the other at 66MHz. So, that not only means that you reduce bus contention, it also means there is a fair bit of bandwidth. On top of which, we don't know how much video RAM there is. If it's 128 MB per G/VPU, which is a definately possible, texture caching won't be that big a problem. Further more, I believe this is for simulations, where the emphasis is on high res and polygons over texturing.

EDIT: I'm copied here something instead of other comment...

Um... huh?
 
I still don't understand something: how can be much faster this card using one single stupid slow PCI slot?
How much faster is the GF4Ti 4600 using the same slow AGP bus as the 8500? And how much faster is the 9700 than the 4600? Bus speed isn't everything; in fact, it seems to be a relatively minor issue from this layman's perspective.

Why wouldn't this company be using ATi's AFR (alternate frame rendering) method, rather than patented SLI? I suppose the delay of four separate renderers would be a bit much, as even the MAXX was supposed to have a delay equivalent to triple buffering. So we're looking at a delay of 3*triplebuffering (something like 180ms, IIRC)?
 
Chalnoth said:
My only gripe would be with the relatively inaccurate rendering of the Radeon 8500 (in comparison to the GeForce3/4 cards, and apparently it's younger sibling, the R300).

Remember the same chip is used in the firegl variants - there are alterations tha can be made for increased accuracy.

Pete said:
Why wouldn't this company be using ATi's AFR (alternate frame rendering) method, rather than patented SLI?

Like I said, I bet they are using more than just one board at a time - or at least have configurations which use multiple boards, in which case AFR wouldn't be a good solution. You shouldn't get so hung up on 3dfx's 'SLI' terminology - scanline interleaving is probably prevelent in solutions like this and is also in operation in standard PC (albeit high end workstation) boards such as Intense3d/3Dlabs Wildcat boards.
 
ERP said:
This doesn't work because transparencies generally do not render Z, so you can't recombine the seperate scenes and have the transparencies correctly sorted.

It will most likely either work in tiles or scanline interleaved (ala 3DFX).

It's a problem to be overcome, not an impossibility. I doubt it would take all that much memory/processing power to store those polygons that won't merge properly.

For example, there are some framebuffer techniques that actually use a separate framebuffer for each polygon, and later combine them for the final output. It's obvious that doing this is impossible with the 4-Radeon setup, but I should think that a similar variant would be an optimal rendering scenario.
 
That's cool. It's a very legitimate use for the technology. I hope nobody here thought it would be used for games.
 
The 2 notches on the right means it's a 33MHz 64-bit card. If it didn't have the notches it would be a 66MHz 64-bit card.
 
> The 2 notches on the right means it's a 33MHz 64-bit card.
> If it didn't have the notches it would be a 66MHz 64-bit card.

Hmm, I have to disagree.

PCI edge connectors can be keyed for 3.3v-only, 5v-only, or 'universal' (supports both.)
PCI v2.2 @ 66MHz *requires* 3.3v operation (5v not supported.) PCI v2.3 has the same requirement, if I'm not mistaken.
PCI 33MHz will work at either 3.3v or 5v signalling.

Many people on forums.2cpu.com found out (angrily) that a 3.3v-keyed PCI card does *NOT* necessarily support 66MHz.

32-bit vs 64-bit operation is *independent* of the voltage-signalling levels. I.e., you can have any combination of 33/66MHz and 32-bit/64-bit. (For example, a 32-bit 66MHz 3.3v PCI adapter is perfectly legal.)

<<< asicnewbie nervous waits for some PCI guru to take him to school on his newbie-post >>>
 
a few points:

1) I'm not sure that is a PCI slot. The pictures not really good enough to say. Considering this is for Simulation stuff there's no reason it has to be any normal standard.

2) The chip by the edge connector must be a bridge of some kind. I expect it has 4 AGP busses on it's back side to talk to each of the Radeons. AGP only allows 1 thing on each bus (electrically).

3) Bus bandwidth might not be an issue is the geometry is fairly static and can be loaded into graphics memory. It could just need to work display lists quickly.

4) Notice that there are two off board connectors on the top-left. These could be another datasource to keep the thing chugging.

Basically this thing is very custom. The normal rules dont apply.
 
"This board, made by CAE combines four Radeon 8500 GPUs onto a single PCI board. It's designed for workstation markets to accelerate complex rendering tasks. A version based on the 9700 will be available this fall."

:)
 
I'm not sure that is a PCI slot.
You think it's a VESA slot instead then? ;) Seriously though, ExtremeTech (who posted the picture) said "PCI board" but if you look at a R300 chip against an AGP slot:

DSCF0028.JPG


the chip length (by my rough eye-calcs) is about 5cm in length. Using another dodgy round of eye-calcs, I'd say the slot on the multichip board is around 10~12cm and that seems very long for a PCI slot.

Also note that the key in the slot is where you'd roughly expect it to be for a 5V connection, but there doesn't seem to be one for the expected 64-bit....unless, it is a 3.3V card and the key slot on the right is for the 64-bit section. In which case, where is the key slot for the 3.3V connection?

Edit: A little bit of Photoshop work...

card_closeup.jpg


I now think it is a "sort-of-universal" 64-bit PCI card. If you look carefully there are 3 key slots, and I suspect that the one on the far left is the 3.3V key, and the next two are the 5V and 64-bit key slots. The specification says that there are 11 pins between the beginning of the left of the slot before the 3.3V key slot. Then there are 35 until the 5V one and then another 11 between the 5V and 64-bit key slots. The rest of the slot until the end of the 64-bit section is 31 pins.

If you look carefully, the length of the connector edge between the above key slots does seem to fit this pattern.
 
Neeyik said:
I'm not sure that is a PCI slot.
You think it's a VESA slot instead then? ;) Seriously though, ExtremeTech (who posted the picture) said "PCI board" but if you look at a R300 chip against an AGP slot.

I think he meant it may be a PCI connector....but that doesn't necessarily mean it uses a PCI interface...
I know AOpen had some extra (don't remember name) port for example on their MoBo's.(the i815 was where it came I think....I owned one)
It wasn't used so to speak but added for DIY'ers to make an own card for whatever reason they wanted to...and hence I doubt it used the specs originally thought of for that port.(I honestly don't remember what it was...but AMR/CNR or ISA turned 180 degrees IIRC...)
So it's quite possible they've used a PCI slot,but use some other way of "talking" with it...
 
Well...for most companies the initial cost ins't very important if it saves them cash along the line...
It can very well be a normal PCI slot....doesn't mean it uses the same type of communication a PC would...
Since that card is very unlikely to be used by anyone outside its specific target group I don't see anything about it that'd rule it out tbh...
Using existing HW that you can buy for less and improving what goes on "behind the scenes" is not a scenario I personally would see as strange...
 
In case this is related

http://www.warp2search.net/article.php?sid=5852&mode=thread&order=0

Here's a partial quote.

"On July 23rd, 2002 the PCI-SIG, the Special Interest Group responsible for PCI, PCI-X and PCI Express industry-standard I/O technologies, announced that its board of directors has approved the official public release of the protocol portion of the PCI-X 2.0 specification. The board also approved the posting of the ‘release candidate’ for the electrical portion of the PCI-X 2.0 specification to the PCI-SIG web site. Together, these two specifications provide all of the information that silicon and systems engineers need to begin their PCI-X 266 and PCI-X 533 product designs today. The electrical portion of the PCI-X 2.0 specification is in the final stages of validation to ensure that the specification meets rigorous engineering standards. The PCI-SIG will release the electrical portion upon completion of this validation process in the coming weeks."
 
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