Cell @ Spring Processor Forum 2005

[one]

http://pc.watch.impress.co.jp/docs/2005/0523/spf04.htm
has many slides from the Cell presentation @ Spring Processor Forum 2005. It focuses on Cell as an embedded processor. (Is it only me that's noticed Jim Kahle always wears the same clothes?)

 

[JF_Aidan_Pryde]

Great find. The "Applicat Specific Acclerator" model sounds like fun. The OS turns each SPE into a mini-ASIC.

 

[ShootMyMonkey]

http://pc.watch.impress.co.jp/docs/2005/0523/spf04_05.jpg
Up to 16-way for the SPEs? I guess when you're in-order, it's about all you can do to hide stalls. And they have dedicated DMACs? Or is it just referring to the fact that they each have their own priority queue for DMA requests?

 

[Gubbi]

http://pc.watch.impress.co.jp/docs/2005/0523/spf04_05.jpg
Up to 16-way for the SPEs?

All it means is that since each SPU is dual issue, the whole system (excluding the PPE) can issue 16 instructions per cycle.

I guess when you're in-order, it's about all you can do to hide stalls. And they have dedicated DMACs? Or is it just referring to the fact that they each have their own priority queue for DMA requests?

Each SPE has a 16 entry DMA queue

Cheers
Gubbi

 

[Npl]

http://pc.watch.impress.co.jp/docs/2005/0523/spf04_05.jpg
Up to 16-way for the SPEs?

All it means is that since each SPU is dual issue, the whole system (excluding the PPE) can issue 16 instructions per cycle.i

Since there is only one Pipe capable of SIMD Instruction( 8 for 8 SPEs), "up to 16-Way 128Bit SIMD" would be plain wrong.

Could also mean that it could use 16 8-Bit Values in a SIMD Operation?

 

[JF_Aidan_Pryde]

http://pc.watch.impress.co.jp/docs/2005/0523/spf04_05.jpg
Up to 16-way for the SPEs?

All it means is that since each SPU is dual issue, the whole system (excluding the PPE) can issue 16 instructions per cycle.

I think it's refering to how finely the SIMD unit can operate. 16-way being 16 Chars/8-bit words in one cycle.

I guess when you're in-order, it's about all you can do to hide stalls. And they have dedicated DMACs? Or is it just referring to the fact that they each have their own priority queue for DMA requests?

Each SPE has a 16 entry DMA queue

DMA engine with 16 entry queue no?

 

[Panajev2001a]

http://pc.watch.impress.co.jp/docs/2005/0523/spf04_05.jpg
Up to 16-way for the SPEs?

All it means is that since each SPU is dual issue, the whole system (excluding the PPE) can issue 16 instructions per cycle.

I think it's refering to how finely the SIMD unit can operate. 16-way being 16 Chars/8-bit words in one cycle.

I guess when you're in-order, it's about all you can do to hide stalls. And they have dedicated DMACs? Or is it just referring to the fact that they each have their own priority queue for DMA requests?

Each SPE has a 16 entry DMA queue

DMA engine with 16 entry queue no?

Yes, each SPE has a DMAC.