The Unreleased CPU Thread

Discussion in 'PC Industry' started by Raqia, Sep 2, 2012.

  1. Raqia

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    This thread is a discussion of unreleased CPU architectures and revisions. In no particular order:

    *** Rock ***

    By far the most interesting to me is Sun's Rock processor with its leap-frogging run-ahead thread design to deal with memory fetch stalls:

    Ars Technica Article
    Paper about run-ahead
    Sun Presentation 1
    Sun Presentation 2

    Is there any hope that something like run-ahead will make it into an actual CPU someday? One of the co-authors in the second paper was from Intel...

    *** Tejas & Jayhawk ***

    Intel's 40-50 stage pipeline revision of netburst:

    Wikipedia article
    Tweakers article

    Looks like this was cancelled right around tape-out! If there's a major breakthrough w/ materials, and we're looking at easily implemented terahertz transistors, maybe Intel will revisit this design... :)

    *** "K9" ***

    An 8-issue successor to K8.

    Anandtech blurb

    This was rumored to have been cancelled because it made too many sacrifices to single-threaded performance and was consuming too much power.

    *** AMD Montreal ***

    An octal core K10 variant, with 1MB of L2 Cache per core instead of 512k intended for server side products. Replaced by Istanbul and MagnyCours.

    Old roadmap

    *** Bulldozer V1, Fusion V1 aka Swift, Komodo ***

    It seems that the Bulldozer which was released in October of 2011 was actually the second version of the CPU, so the delay of BD was actually the cancellation of the release of the first version. Same with Fusion which supposedly had a separate BD CPU and ATI GPU die joined in an MCM. The MCM / BD core design was canned in favor of a single die with STARs cores for Llano.

    Old roadmap
    Old presentation

    Komodo was pildriver core based CPU with up to 10 cores; it's been replaced by Vishera which sports 8 cores. This isn't so much a cancellation as a reworking of the CPU to be compatible w/ existing platforms.

    Techpowerup article

    *** Witchita & Krishna ***

    Quadcore version of the bobcat on 28nm with turbo boost.

    Extremetech article

    *** AMD Mustang ***

    suggested by: fellix 09/02/12

    Unreleased processor supporting up to 4MB L2 cache and 2 extra pipeline stages for higher clocks. It seems the code names "Palomino" and "Thoroughbred" were a play on this name.

    Dslreports article

    *** EV8 & Tarantula ***

    suggested by: Gubbi 09/03/12

    Alpha's unreleased 8 issue monster and its successor.

    RWT Exposé
    Paper about Tarantula

    *** Timna ***

    suggested by: swaaye 09/03/12

    Intel's MediaGX, a Celeron with onboard GPU. This was designed by Intel's Haifa team.

    Wikipedia Article
    Overclockers Article
    cpu-world forum with engineering sample

    *** AMD K7 Server, 90nm refresh ***

    suggested by: hkultala 09/03/12

    *** Via / Cyrix Joshua ***

    suggested by: kalelovil 09/05/2012

    Cpushack.com link
    Karbosguide.com link
    PCWorld article

    "The Joshua (Jalapeno Core) was in the works at Cyrix as they were sold to VIA in 1999. The Joshua was a socket 370 CPU with support for RDRAM and onboard MPEG decoding. It would have used a 133MHz bus. It had a 64KB L1 cache and a unique scratch pad RAM area for the CPU. It supports full MMX and the original 3D Now! It was released in prototype form only." -cpushack

    Media GX2? I wonder what the scratch pad ram's all about. The RDRAM controller was a pretty bad call for Cyrix unfortunately.

    *** Havendale / Auburndale ***

    suggested by: kalelovil 09/05/2012

    Nehalem w/ MCM graphics.

    Nehalem variants wikipedia page
    -------------------------------

    These are all the ones I can think of right now, please add if there's an interesting one missing!

    (On a side-note, AMD's been executing much better recently, probably as a result of Dirk Meyer's cutting back of lots of unfeasible projects which is only being felt now.)
     
    #1 Raqia, Sep 2, 2012
    Last edited by a moderator: Sep 7, 2012
  2. I.S.T.

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    The roadmap before Tejas' cancellation was set to transition to Nehalem eventually anyway. It was merely accelerated due to the dual 90 nm and Prescott troubles.
     
  3. fellix

    fellix Hey, You!
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    One code-name I remember is "Mustang" by AMD. It was supposed to be a follow up of the first K7 line, but targeted for the server market, with a ton of off-chip cache, very wide pipeline and some SMT tech involved. K8 came after that and I guess most of the ideas got in there, minus the SMT and the external cache.
     
  4. Raqia

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    Nehalem was a codename for two different products I believe, one of which was cancelled.
     
  5. Gubbi

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    Most interesting processor that never was: The Alpha 21464.

    An eight way superscalar out of order execution with SMT with an ambitious vector unit integrated with the core, Tarantula.

    The vector registers were 128 doubles wide (eight kilobits). 32 double precision floating point ops could be done per cycle.

    The really interesting bit is the gather/scatter implementation. Vector loads and stores went straight to a 128 banked L2 cache. The vector load/store unit could generate 16 adresses per cycle and reading 16 independent cache lines from the L2 provided none of the cache lines had conflicting banks.

    - A 2002 design that make Haswell look absolutely feeble.

    PDF on Tarantula here.

    Cheers
     
  6. swaaye

    swaaye Entirely Suboptimal
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  7. 3dcgi

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  8. hkultala

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    AFAIK Mustang was supposed to be exactly same core as palomino, but with much bigger l2 cache.
    All the changes AMD designed for Mustang (except the big cache) went into Palomino, palomino is just "mustang on a diet".

    I think what you have heard are not about Mustang but some other unreleased chip(the K9 discussed in original post?)


    Another unreleased product from AMD is the server version of the original K7; The K7 chip itself could support L2 caches for up to 4 MiB, but they only released the desktop product with 512 kiB L2 on Slot A

    The server model would have used 2-4 MiB L2 cache and Slot B.
     
    #8 hkultala, Sep 3, 2012
    Last edited by a moderator: Sep 3, 2012
  9. swaaye

    swaaye Entirely Suboptimal
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    I suppose that the limited gain that more L2 cache brings Athlon XP (ie Barton) and the 180nm process probably killed Mustang.

    One certainly finds more search results with that spelling. ;) I couldn't remember what it was called and finally stumbled on that Overclockers.com piece.

    Photos of prototype.
    http://www.cpu-world.com/forum/viewtopic.php?t=11663
     
  10. Thorburn

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    Few people at work have Timna's still. Was trying to Get one for a while but those who kept them are all too sentimental.
     
  11. kalelovil

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    #11 kalelovil, Sep 5, 2012
    Last edited by a moderator: Sep 5, 2012
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