Cell details (Nikkei Electronics)

[one]

is it true cell first born may have only 4 spe?

It's very unlikely as Kutaragi himself basically ordered it to be 8, though the clock speed may be downgraded. Also, I don't understand why the dev board has 2 Cell processors... is it only for the dev kit? Everything will be (hopefully) disclosed in the next month!

 

[nAo]

We started with 32 SPEs..then we downgraded our (too optimistic!) expectations to 8 SPEs...what next? 4 SPEs at 3 Ghz?

 

[pahcman]

2 cell dev?

1 cell cpu 1 cell gpu?

4 spe @ 3ghz is how good?

wow 32 spe on 1 chip?? that is some expectations!

 

[ChryZ]

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http://techon.nikkeibp.co.jp/article/HONSHI_LEAF/20050223/101976/
translated by excite.co.jp

Nikkei electronics February 28, 2005 issue
Cover Story
Cell birth

"I want ..computer architecture.. to start a revolution. "--Finally, next generation microprocessor "Cell" by which vice president Sony's Takeshi Hisashi Taragi managed leading took off the veil. The height of the extendibility in addition to an overwhelming operation performance of 256 GFLOPS draws an existing technology and a line by 4GHz operation. It approaches the whole content of Cell by the developer along with a technological thesis.

< The aftereffect to the industrial world is foreseen >
The game machine to the starting point
It runs through by the next ten years.
Can Sony computer entertainment (SCE) achieve the common sense breaking of the third times?--｡It is 1994 first. The fresh force's entry succeeded in introducing to the family-use game machines market said to be impossible, and becoming a major game machine by a new medium named CD-ROM ahead of overwhelming strength of Nintendo and Sega Enterprises. The second is 2000. An immovable position in the game machine industry though the feat that included a state-of-the-art semiconductor technology was accomplished, and it criticized to natural family-use game machines, "Masterpiece principle" to use a withering technology was secured.
Are there three-degree what is twice?Tecoma that SCE draws out as the next feat is next generation microprocessor "Cell" in 2005. Cell is not LSI that assumes only the game machine. It aims at installing from the home server to a television, a portable equipment, and the workstation.

< The lamplight also solves architecture >
In the buried gene
It evolves to a free transforming.
The maximum technical feature that "Cell" has is in the point changed by a free transforming the performance of the microprocessor according to the usage of the equipment by increasing and decreasing the number of signal processing processors that call "SPE(synergistic processing element)", and connecting Cell mutually by a very high-speed interface.
Cell of the first generation that accumulates eight SPE is made a starting point based on such a feature, and the kind that changes the composition as the number of SPE of each usages is changed is progressed there one after another ahead. The lamplight also solves an internal structure of an experimental chip of Cell clarified this time, and the gene that the development formation built in comes to the surface clearly for that.

< The developer voluntarily spells it >
Nine processors were accumulated.
Next generation's general purpose MPU is developed.
Szo Masakazu
Sony computer entertainment
Semiconductor business headquarters Microprocessor development department Director
James Kahle
U.S. IBM Corp. and IBM Fellow
Broadband Processor Technology Microelectronics Division
Ma Biu
U.S. Toshiba America Electronics Components,Inc.
Director of Engineering STI Design Center
Next generation's general-purpose microprocessor "Cell" was developed. 64 bit CPU core based on the "Power" architecture of U.S. IBM Corp. was accumulated and the register in 128 bits was accumulated in single-chip with nine processor groups in total that consisted of eight independent signal processing processors "SPE(synergistic processing element)" that treated. The special memory of 256 Kbyte that was called a local store was built into each SPE. Besides this, each instruction 32 Kbyte cash, the data cache, and the second cash of 512 Kbyte were prepared in CPU core.

< Hear it in the top >
" "Because of challenge of one age degree it
Hisashi Taragi Takeshi

くたらぎ Tendon
After it joins Sony in 1975, it is wandering in the 1st development department, the 2nd development department, the information processing laboratory, and General Institute. The entry into the game machine market was invested in management petitioning directly and voluntarily, and the Sony computer entertainment was established. The development of "PlayStation" and "PlayStation 2" was commanded. It is this company now. It is President and Representative Director, group CEO, and it serves as the vice president and COO of Sony. It is asserted, it is "I am an engineer" now.
- This continuation can be read by the issue for 28 days February, 2005 of the Nikkei electronics.

http://techon.nikkeibp.co.jp/article/TOPCOL_LEAF/20050224/102031/
translated by excite.co.jp

Are the number Cell with built-in of SPE eight why?
2005/02/25
Shallow view Naoki(editor in chief of Nikkei electronics)

Next generation microprocessor "Cell" that Sony, Sony computer entertainment (SCE), Toshiba, and U.S. IBM Corp. developed catches the architecture of the multi core type. It is 8, and the core for the signal processing processor that CPU core of the Power type calls SPE in one and it is nine multi core structures in total. Then, the number of SPE is regulations — in 8 pieces from what background. —｡

The critical factor is in the point where to suppress the area of the chip in the design of the semiconductor by using what microfabrication technology. After PlayStation 2 is put on the market, I already want to put the next generation game machine to practical use for SCE that five years pass slowly. Then, it is 90nm rule as for a semiconductor technology that is stabilizing and is state-of-the-art now. Then, an appropriate area of the chip is − the cost in how many though manufactured from 90nm. −｡The initial goal seems to have been 185mm2. However, it was understood to exceed this target value greatly, and the development team examined assumption as six SPE if becoming it when eight SPE was built into.

Appearing here is that Takeshi Hisashi Taragi. It is in the seat of the vice president of Sony, and is leading a real parent of the play station that was able to be known not to say and this project now. Rejection, "If it is neither the world of the computer it is nor an involution of two, this is aesthetics", and the proposal ..this proposal.. are repelled in a single phrase, and the Mr. Hisashi Taragi has been decided to this composition finally. Giving priority to sticking to when it is painful is Mr. Hisashi Taragi's opinion though the size of the chip grew more than 221mm2 and the schedule. The whip is flicked to the place where the site seems to be exhausted, and the ideal is pursued. --I feel the essence of MOT(management of technology) in such severe technological management.

Well, the Nikkei electronics published the feature article that made this Cell a theme by the latest title (issue on February 28, 2005). It is time February 7 in the United States that Cell was announced. An urgent feature was united from the desire that it wanted to deliver latest information in detail during freshness. The engineer of SCE/International Business Machines Corporation/Toshiba that was involved in development in addition to the interview of Mr. Hisashi Taragi composed of 33 pages together with the contribution thesis. I think that it can peruse it by all means. It would be greatly appreciated if it could be actually felt that the technology driver is changing from the mainframe into the game machine.

http://techon.nikkeibp.co.jp/article/TOPCOL_LEAF/20050225/102098/
translated by excite.co.jp

"Cell":LSI that "Self agenda" brought it forth.
2005/02/25
Yosuke Mochizuki = Nikkei Japan Microdevice

The feature of "Cell" was united by the latest title of 'NIKKEI MICRODEVICES'. The title is "Ambition of the computing revolution and 'Cell'. "It is a remark of Mr. Hisashi Taragi that feels while imagining the appearance for Cell to be going to proliferate in the future and to improve the influence power to the society because it renews now though I would like seeing the magazine for details of the processing technology and architecture it.

It was in March, 2001 that announced the joint development of "Cell" four years ago. It interviews Sony computer entertainment president Takeshi Hisashi Taragi at the end of 2000 immediately before that. This Mr. was multiusing word "Self agenda". It is meant to decide it should have to be own (self)(agenda). It is not a route that others paved, and the scenario is voluntarily drawn.

There was certainly an age that was able to exist as a semiconductor manufacturer even if the vector was not voluntarily decided when looking back on the semiconductor industry. It is an age when everyone can obtain the profit if walking in the route that advanced LSI manufacturer in the United States paved. Concretely, information on Intel that led the PC industry was acquired very early, and LSI manufacturer in the world competed whether to include it in its own product specification in 1990's. However, much of LSI manufacturer in the world has hesitated in the age that the driver of the semiconductor shifts from PC to post PC.

Mr. Hisashi Taragi who was strongly appealing for "Self agenda" under such a situation is commenting as follows at the same time. When this magazine questioned on the forecast in the future of the semiconductor, it was assumed that it was not significant to the forecast in the future, and there not a certainty either, and made remarks, "The forecast will be voluntarily made in the most exact future" (this Mr.).

This Cell looks like LSI that "Self agenda" and "Will voluntarily make it in the future" brought it forth.

 

[nAo]

2 cell dev?

1 cell cpu 1 cell gpu?

First and last warning..if I read another time '1 cell gpu' I'm going kill someone (I'm joking pahcman..but never existed a cell gpu and never will)

4 spe @ 3ghz is how good?

It's good but it doesn't seem to be much better than what we are expecting from xenon leaked specs. Nothing wrong with that, Xenon could be a more powerful system than PS3, even if it seems PS3 should be more capable to run near its theoretical peak performance, imho.

wow 32 spe on 1 chip?? that is some expectations!

Remember the old 1 Teraflop/s times?

 

[j^aws]

what happen to sony highly advanced 65nm tech? 90nm isnt what intel already have today? what happen to the ps3 cell was from scratch a 65nm design? why did kk say a dream??

i want edram!
...

A summary of what I've gathered so far...

There are basically two distict types of 65nm process...

1. 65nm SOI
2. 65nm bulk-CMOS

SOI is basically more power efficient and will clock higher than bulk-CMOS. Now apparently there are some issues with eDRAM and SOI. One of the reasons why eDRAM may have been ditched from CELL. However, they could push 90nm SOI further as it still has alot of headroom left than start a new 65nm SOI process for mass production of CELL.

If eDRAM is used then it's likely to be on 65nm bulk-CMOS and not 65nm SOI, which the SONY-TOSH fabs are still geared towards for the GPU.

...
is it true cell first born may have only 4 spe?

Kutaragi seems to think otherwise!

 

[Shifty Geezer]

As I read it, KK's expecting a 1:8 Cell. They can't manage this at 65 nm so they'll stick with 90 nm. First yields of this chip were up at 5.3 GHz so 4 GHz is possible. The processor is as big as IBM ISSCC showing, which means if there's two, there's going to be 2 might slabs of silicon in the PS3 as well as the GPU. Suggests maybe a single Cell system? However KK seems happy with the yields, as though the design is fulfilling his requirements (save the one teraflop promise ).

This to me points to something like PS3 having
74% chance of one 1:8 Cell
24% chance of two 1:8 Cells
2% chance of something else

 

[Titanio]

As I read it, KK's expecting a 1:8 Cell. They can't manage this at 65 nm so they'll stick with 90 nm. First yields of this chip were up at 5.3 GHz so 4 GHz is possible. The processor is as big as IBM ISSCC showing, which means if there's two, there's going to be 2 might slabs of silicon in the PS3 as well as the GPU. Suggests maybe a single Cell system? However KK seems happy with the yields, as though the design is fulfilling his requirements (save the one teraflop promise ).

This to me points to something like PS3 having
74% chance of one 1:8 Cell
24% chance of two 1:8 Cells
2% chance of something else

Except, "officially", none of what's being said in these articles is related to PS3?

Also, where did the 4 SPE at 3Ghz speculation come from? Just a guess, or is it in the article somewhere? That said, even a 4 SPE PE at 3Ghz would yield 120 Gflops, or roughly 50% more than the rumoured tri-core Xenon spec.

 

[nAo]

Also, where did the 4 SPE at 3Ghz speculation come from?

It comes from me, it's just a joke!!
But it could be real..who knows

 

[passerby]

Let me give a stab at guessing.

Guess #1
The usual, 1:8 configuration.


Guess #2
This one arises from the confusion last year at the RDRAM conference, when 3 major RDRAM suppliers announced that they will be concentrating on 128mbit chips in 2005 due to 'requests from the main consumer'. Since KK himself attended the conference and even gave a talk, it's an easy guess as to who the 'main consumer' is. The speculation was that PS3 will be moving from the popular guess of "4 256mbit chips for 256MB @25Gb/s" to "8 128mbit chips for 256MB @51Gb/s".

So working with this particular speculation now, my second PS3 guess is :
2 1:4 Cell CPUs, 4 128mbit RDRAM chips to each CPU, aggregate bandwidth 51Gb/s.

Much more realistic than the 2 1:8 CPU guess. One more PPE to handle SPE-unfriendly logic. A memory configuration that supports the events of last year's RDRAM announcments. A memory bandwidth that isn't too unrealistic, considering the bandwidth of current top-end graphics cards. Far enough from being a fanboi's dream, no?

 

[nAo]

So working with this particular speculation now, my second PS3 guess is :
2 1:4 Cell CPUs, 4 128mbit RDRAM chips to each CPU, aggregate bandwidth 51Gb/s.

Where does the GPU fit in that figure?

 

[one]

The speculation was that PS3 will be moving from the popular guess of "4 256mbit chips for 256MB @25Gb/s" to "8 128mbit chips for 256MB @51Gb/s".

Well the rumor recently faded out... Even Hiroshige Goto who started the rumor withdrew it by stealth!

 

[passerby]

Well the rumor recently faded out... Even Hiroshige Goto who started the rumor withdrew it by stealth!

You're right, and I even got the 128,256,512 numbers mixed up.

 

[version]

on ps2, VU1 has 0.5-1GB/s memory bandwith
SPE 10+ times faster than VU1, hence for every SPE must have 5-10 GB/s
for 8 SPE+PPE 50-100GB/s

25 GB/s xdr not enough, 50 the minimum...

variations:

1. 1cell with 4 SPE , this is suxxx
2. 50GB/s and 512 GB xdr, too expensive but cool
3. 25 GB/s xdr and 25GB/s from GPU's ram, bizarre and GPU with 50GB/s xdr expensive too
4. 2 cell with 4 SPE 2*25GB/s and GPU 25GB/s
, complicated but 5 GHZ not impossible

other possibility ?

 

[Panajev2001a]

on ps2, VU1 has 0.5-1GB/s memory bandwith
SPE 10+ times faster than VU1, hence for every SPE must have 5-10 GB/s
for 8 SPE+PPE 50-100GB/s

25 GB/s xdr not enough, 50 the minimum...

variations:

1. 1cell with 4 SPE , this is suxxx
2. 50GB/s and 512 GB xdr, too expensive but cool
3. 25 GB/s xdr and 25GB/s from GPU's ram, bizarre and GPU with 50GB/s xdr expensive too
4. 2 cell with 4 SPE 2*25GB/s and GPU 25GB/s
, complicated but 5 GHZ not impossible

other pissibility ?

Let's look at it this way (looking at storage capabilities of the two units)

VU1 = 16 KB of Istruction Memory + 16 KB of Data Memory + 32x128 bits registers + 16x16 bits Integer registers.

SPE = 256 KB of combined Instruction and Data Memory + 128x128 bits registers.

I see one of them having a much higher advantage, without even touching the nice DMA mechanism each SPE has.

 

[Shifty Geezer]

on ps2, VU1 has 0.5-1GB/s memory bandwith
SPE 10+ times faster than VU1, hence for every SPE must have 5-10 GB/s
for 8 SPE+PPE 50-100GB/s

Is this an issue with streamed/piped SPUs? You can feed one SPU at 10 Gb\s, then pass it's data onto subsequent SPUs for processing. Passing data between SPUs doesn't need the external bandwidth does it?

 

[version]

if you read vertexstream (16bit,y,z,normalX.Y,Z,uv1,uv2=128bit ,16 byte)
and rotated, projected vertexs that about 10 cycle on SPE
then 1 SPE load 6.4 GB/s data from memory, 4 SPE kill the xdr bandwith
what doing other 4 SPE and PPE ?

 

[j^aws]

if you read vertexstream (16bit,y,z,normalX.Y,Z,uv1,uv2=128bit ,16 byte)
and rotated, projected vertexs that about 10 cycle on SPE
then 1 SPE load 6.4 GB/s data from memory, 4 SPE kill the xdr bandwith
what doing other 4 SPE and PPE ?

I think you should be able to get away with it. Remember the L2 - 512 KB cache is on the EIB ring bus feeding SPEs. The L2 is a Streaming Cache. You should be able to use it as a Stream Register file equivalent.

If the CELL is 1:8, then can't you pipeline 8 SPEs, i.e.

[XDR]<--->[L2-Cache]--->[SPE:1-7]--->[SPE:8]--->[GPU]---> Output
            ^__________________________|__________|

Using L2 and pipelining SPE:1-8 and GPU would save bandwidth and wouldn't need ~50 GB/s XDR because you have ~200 GB/s EIB ring bus bandwidth, no?

 

[Shifty Geezer]

That's what I'm thinking. Load SPU1 up, it does it's thing passes the data to SPU2 which does it's thing, passing to SPU3... Dunno what kind of programs you could get running in such an method but it ought to be memory bandwidth efficient.

 

[j^aws]

That's what I'm thinking. Load SPU1 up, it does it's thing passes the data to SPU2 which does it's thing, passing to SPU3... Dunno what kind of programs you could get running in such an method but it ought to be memory bandwidth efficient.

You use a Stream programming model, e.g. Cg, Brook on a Stream processor, e.g. Imagine or CELL,

http://cva.stanford.edu/imagine/index.html