Can AMD GPUs implement 'hardware' fixed function pipelines through firmware?

[3dilettante]

I wasn't sure where else to put this, but an interesting side note on the use of custom processors for media blocks is that Nvidia is apparently replacing a workhorse custom processor (Falcon) used in various engines and media blocks with a new core based on the open RISC-V architecture. I suppose it might fit somewhere in a future Nvidia speculation thread, but which one is not clear.

http://www.lowrisc.org/blog/2016/07/notes-from-the-fourth-risc-v-workshop/

NVidia RISC-V evaluation story: Joe Xie

• Want to reproduce the existing NVIDIA falcon CPU with a new ISA
• Falcon - FAst Logic CONtroller. Introduced over 10 years ago and used in more than 15 different hardware engines today. Low area, secure, flexible. 6 stage pipeline, variable length instructions (proprietary NVIDIA ISA).
• The next generation for Falcon is needed for higher performance and rich OS support. Old Falcon is 0.67 DMIPS/MHz, 1.4 Coremark/Mhz
• Options were to buy access to a current architecture (MIPS, ARM, others) or build (move to RISC-V or improve Falcon). Obviously, they elected to move to RISC-V. The fact the ISA is extensible is a key advantage. Want an area of less than 0.1mm2 at 16FF.
• NV-RISCV is 5 stage in-order issue, out-of-order execution. It has a in-order write buffer. No FPU. Makes use of an MPU with base and bound protection. It will initially be added to the Falcon as a 2nd core to provide easy backwards compatibility.
• Area for 16FF: Falcon 0.03mm2 vs Rocket 0.055mm2 vs NV-RISC-V 0.05-0.06mm2.
• Did a lot of cache optimisations to tolerate large latency. Store buffer, write merging, line-fill buffer, victim buffer, stream buffer.
• Areas of interest include toolchain (for automotive, debug, performance tuning, flexibility, ilp32/ilp64). Also security (crypto instructions and extensions), and adding cache manipulation instructions.
• Question: why design your own core rather than use an existing one? Answer: after evaluating the options, it made the most sense. The motivation to go to RISC-V was technical as well as influenced by cost.

Some googling brought up further descriptions of places where the core wound up in parts of various Nvidia GPUs in the following:
https://media.readthedocs.org/pdf/envytools/latest/envytools.pdf