Athlon64 and PCI Express

[3dilettante]

I've been thinking about the transition from AGP to PCI Express as it pertains to the on-die memory controller of the AMD 64 chips.

One of the features of this arrangement is that the AGP GART is on the die as well, which doesn't seem to be a problem at the moment, but what would happen when PCI Express takes over?

Does PCI Express have a similar need for a GART on die, and will this wind up requiring another stepping of AMD 64 chips just to support new PCI Exp. video cards?

Will the AGP GART become a silicon appendix, existing only as dead weight rarely used in the real world (assuming it doesn't take forever for AGP to be phased out).

I know an easy sarcastic response would be that using X86 is enough dead weight as-is, so why worry about a little more, but seriously...

In addition, I for one kind of feel let down about the Opteron and A64 memory controllers. While they are low latency and supposedly operate at processor frequency, they only seem to be really fast "dumb" memory controllers. One would think that with a 2+Ghz A64, AMD could think of something extra for the memory controller to do with what could be dozens of spare cycles between every memory operation.

 

[pcchen]

To my understanding, PCI Express does not use GART, but use PAT (page attribute table). PAT is supported only in P3 or newer CPUs, so it was not an option for AGP.

 

[jpaana]

One of the features of this arrangement is that the AGP GART is on the die as well, which doesn't seem to be a problem at the moment, but what would happen when PCI Express takes over?

Actually both AGP and PCI-X are totally external from the CPU core, connected with HyperTransport links.

For example the AMD's own Opteron chipsets (http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_4699_7980^4741^4931,00.html) consist of:

The AMD-8111 HyperTransport I/O Hub replaces the traditional Southbridge. This component integrates storage, connectivity, audio, I/O expansion, and system management functions into a single device.

The AMD-8131 HyperTransport PCI-X Tunnel is a high-speed device that provides two independent, high-performance PCI-X bus bridges, integrated with a high-speed HyperTransport technology tunnel.

The AMD-8151 HyperTransport AGP 3.0 Graphics Tunnel is designed to communicate with graphics devices on platforms implementing HyperTransport technology. AMD is working with major graphics solution manufacturers on the implementation of the AMD Athlon 64 and AMD Opteron processor-class systems. These systems are designed to support standard AGP graphics cards, including leading-edge AGP 3.0 cards.

So leaving out AGP isn't a problem in any case.

 

[3dilettante]

http://www.digit-life.com/articles2/amd-hammer-family/

According to this site at least, the GART and some elements of the PCI to PCI bridge reside on the CPU die.

"AMD integrated the Graphics Address Remapping Table (GART) into the controller. Now there is an additional data transfer stage with the Hyper Transport between the memory and video adapter - but the most difficult work of memory address renaming and request location will be carried out at a much higher speed. As a result, the speed will go up rather than fall down. The memory controller also contains a part of the PCI-to-PCI bridge. That is why almost total control over the data transfer is on the shoulders of the X-bar, an internal processor switch, thus allowing the core fulfill more intellectual work. I wish we knew more about it. It looks like an analogy of the DMA, but on a new level. And it reminds the I2O architecture."

 

[jpaana]

They probably mean the cpu's IOMMU, which is a much more generic concept than AGP GART, but can also work as such. It can map parts from the 52-bit memory physical address space to arbitary 32-bit addresses as seen by 32-bit addressing IO devices, including PCI and AGP. This is basically the same thing AGP GART does, only 32/32 bit translation. It is also used for example by Linux to map scattered pages to be read or written to disk to one larger request seen by the disk controller, so it's quite useful outside AGP as well.

 

[Kaotik]

One of the features of this arrangement is that the AGP GART is on the die as well, which doesn't seem to be a problem at the moment, but what would happen when PCI Express takes over?

Actually both AGP and PCI-X are totally external from the CPU core, connected with HyperTransport links.

You're mixing PCI-X with PCI Express here.
PCI Express is the next gen bus, x16's will replace AGP and x1's traditional PCI's.
PCI-X is practically only faster "traditional PCI", used on server/workstation mobos.

 

[jpaana]

You're mixing PCI-X with PCI Express here.
PCI Express is the next gen bus, x16's will replace AGP and x1's traditional PCI's.
PCI-X is practically only faster "traditional PCI", used on server/workstation mobos.

True, should have read better (and names are too similar anyway). In any case, the same applies to all PCI, AGP, PCI-X and PCI Express, they are all taken care outside the processor. To the processor they all look the same, thanks to the IOMMU and memory mapped IO.