But it is backed up by the huge PHYs evident on Tahiti die shots and Dave Baumann has said here in the forum, that Pitcairns PHYs are just a bit more than half the size or so (per 128bit segment) compared to Tahiti.This was discussed earlier, right? Was the conclusion that fast 386 (Tahiti) IO blocks are larger than slow 512 (based on area of slow IO block of some lower level chip)?
It feels counter-intuitive.
You will probably run into the limits of the memory controller before you hit limits of fast GDDR5 chips. I guess it's close to impossible to hit memory speeds significantly above 6GBps on a Pitcairn style interface no matter what chips you connect to it.And it should be easier to create over-clockable board by populating the PCB with faster spec'ed GDDR5 RAMs, which board partners will love.