Frenetic Pony
Veteran
So, yes, "entire lineup" will be replaced for the 4xx generatio of AMD cards: http://wccftech.com/amd-arctic-islands-16nm-launch-coming-quarters/
AMD: Speculation, Rumors, and Discussion (Archive)
- Thread starter iMacmatician
- Start date
- Status
iMacmatician
Regular
From WCCFTech: "AMD R 400 Series Ellesmere And Baffin 'Arctic Islands' GPUs Taped Out, To Enter Production In 2016."
I think that three FinFET chips in (presumably) 2016 will be quite exciting.
Apple?
I think that three FinFET chips in (presumably) 2016 will be quite exciting.
Frenetic Pony
Veteran
Only 3 GPU's for 4xx lineup, 2 of the 3 taped out http://wccftech.com/amd-16nm-ellesmere-baffin-arctic-islands-taped-out-2016-production/
Guess that means 6 SKU's for the lineup in total? It's very close to what Nvidia's done with Maxwell and everyone seems to like that.
Guess that means 6 SKU's for the lineup in total? It's very close to what Nvidia's done with Maxwell and everyone seems to like that.
Silent_Buddha
Legend
Doesn't seem to be hurting Nvidia at the moment with GM206/204/200 for their discrete GPU line. So, why should it be different for AMD?
Most likely. Apple aren't going with Nvidia anytime soon, unless Nvidia changes its stance on OpenCL or Apple changes its stance on OpenCL. I see neither of those happening in the near future.
Regards,
SB
I guess other reasons come before OpenCL, such as price and reliability. Given my luck, I (still) own two of the mbp which had gpu failure, one with a 8600m (that was repaired) and a 330m, I lost the window offered for the free repair, so I am gonna use some 3rd part service to get it repaired..
Nvidia technically has more than 3 maxwell chips. Even maxwell gen 1 is still pretty modern compared to cards in the AMD line up. Whats AMD gunna do below the 470? rebrand pitcairn again?
That'd be tragically hilarious if they did.
Why would they need more than 3 Chips? Southern Islands also just launched with 3 Chips and the lower segment is decreasing more and more due to igps.
I would expect 1 ~400mm², 1 ~250mm² and one ~125mm² gpu. Just when they try to launch a big gpu like GP100 from the beginning, then it'll be a bit more tricky. But that seems too risky looking at AMDs R&D.
I would expect 1 ~400mm², 1 ~250mm² and one ~125mm² gpu. Just when they try to launch a big gpu like GP100 from the beginning, then it'll be a bit more tricky. But that seems too risky looking at AMDs R&D.
Southern island had huge holes in the performance stack that wasn't filled. Also it didn't release anything below a 7750 which would be like a 470 level card. Not only that but the top chip was only ~300mm^2.
If AMD only makes 2 skus out of each chip. They would only have 6 cards with 3 chips. If they want to sell their top chip for $650, they will have a hard time filling the spaces especially since they desperately need competitive mobile skus if they want to compete at all in that space.
If AMD only makes 2 skus out of each chip. They would only have 6 cards with 3 chips. If they want to sell their top chip for $650, they will have a hard time filling the spaces especially since they desperately need competitive mobile skus if they want to compete at all in that space.
I dunno isn't the nano a new card segment for them ? So I can see the top chip getting 3 bins .
1. Water cooled
2. Cut down air cooled
3 high end bins with a nano size
They could actually just add the nano size to all 3 chips actually now that I think about it.
The hybrid node presents some interesting changes. Marketing-wise, it is two nodes improved over 28nm, although it may be arguably a "traditional" 2x node improvement spread over two generations.
In terms of transistors, FinFET changes the leakage picture massively, and the transistors scaling two nodes should present a significant amount of power headroom despite the lagging metal density.
Anantech's FuryX review tried to estimate the power influence of thermal leakage, with something around .5-1 Watts per degree C with 18W difference going from 40C to 65C. FinFET changes the leakage picture a lot. Planar might have a design accepting static and dynamic consumption in the same order of magnitude, whereas after FinFET it was possible to drop static power by an order of magnitude.
That, coupled with an improvement in active consumption that the foundries seem confident to market like a good node transition (while ignoring that it happened over two generations), could buy AMD a lot given how evident the power ceiling has been as of late.
The lack of 2 nodes of density scaling could hurt the peak resource count, however. FinFET does have proportionately more benefit in a modest clock regime, although AMD could opt to push clocks past the comfort zone when the ability to add resources is constrained like it did with 28nm.
So where GPUs go with a process with a changed physical reality at 14/16nm, where wire scaling is even worse than experienced at 28nm and transistor performance and leakage profiles significantly changed will be interesting.
Are the GPU architectures from Nvidia and AMD significantly more wire-limited than the other, for example?
In terms of transistors, FinFET changes the leakage picture massively, and the transistors scaling two nodes should present a significant amount of power headroom despite the lagging metal density.
Anantech's FuryX review tried to estimate the power influence of thermal leakage, with something around .5-1 Watts per degree C with 18W difference going from 40C to 65C. FinFET changes the leakage picture a lot. Planar might have a design accepting static and dynamic consumption in the same order of magnitude, whereas after FinFET it was possible to drop static power by an order of magnitude.
That, coupled with an improvement in active consumption that the foundries seem confident to market like a good node transition (while ignoring that it happened over two generations), could buy AMD a lot given how evident the power ceiling has been as of late.
The lack of 2 nodes of density scaling could hurt the peak resource count, however. FinFET does have proportionately more benefit in a modest clock regime, although AMD could opt to push clocks past the comfort zone when the ability to add resources is constrained like it did with 28nm.
So where GPUs go with a process with a changed physical reality at 14/16nm, where wire scaling is even worse than experienced at 28nm and transistor performance and leakage profiles significantly changed will be interesting.
Are the GPU architectures from Nvidia and AMD significantly more wire-limited than the other, for example?
Most ultra book use IGP ( from Intel ), some specific low end mobile gpus ( like the 940M, 950M ) ... specific gamers laptop need high end gpu's with a middle end for have a lower price available. better to go with an APU who can compete in this space honestly.. you dont need low end mobile discrete gpu in the notebook space anymore, even middle end start to be questionnable . i dont think gamers laptop sold so much anyway in the other hand.
Let see: 1 sku: R490x-490 second sku: R480x-480, maybe even 460.. last SKU for R460-450-440 ... is it really not enough ? In what is it different of what offer nvidia and AMD since ever ?
Actually, a 400mm² Greenland may not be fast enough to be called a true upgrade from Fiji
Where have you seen it will be only 400mm2 ?..
Last edited:
Jawed
Legend
Don't the newest GPUs, which are mostly "off" in idle and rarely fully on (no matter what the Afterburner readout for GPU usage says) prove that static consumption isn't high performance GPUs' problem? Therefore that gain from FinFET isn't really the reason we'll get more performance.
Sure in an APU this is a big deal, but we're talking 1W - 35W envelopes and battery life. AMD's already demonstrated (with Carrizo) that there are substantially different accessible trade-offs in performance-v-power curves and discrete and APU should lie at the extremes of those trade-offs as far as static leakage is concerned.
Sure in an APU this is a big deal, but we're talking 1W - 35W envelopes and battery life. AMD's already demonstrated (with Carrizo) that there are substantially different accessible trade-offs in performance-v-power curves and discrete and APU should lie at the extremes of those trade-offs as far as static leakage is concerned.
Jawed
Legend
I haven't. This was merely a follow-up comment to the idea of a 3-chip plan others talked about, with the largest being 400mm².
I think we can be certain that AMD has something like a Kepler->Maxwell architectural revision on hand. It's been years in the making. And AMD, if it has a clue, knows that NVidia will be going 500mm²+ in 2016 on FinFET, because NVidia has always gone large. The cancelled node if nothing else should have given both of them much more confidence in the new node because neither of them will be making the maximum possible change going into this node (whereas that might have been the case at 20nm for AMD if the plan for Arctic Islands was originally 20nm + HBM).
AMD made the maximum possible change going into 28nm with Tahiti in terms of GPU architecture, but was at least comfortable with GDDR5 by then. We should be seeing the same this next time around. Waiting until 2017 to put out a 500mm²+ GPU is like pretending that Fiji didn't happen. (Though Fiji seems to me to be an end-of line chip, a bit like Cayman, so one might argue it was originally going to be the 20nm + HBM chip and therefore not 500mm²+.)
Really this all hinges on whether AMD is serious about enthusiast gamers, because there's going to be loads of them ready to buy 500mm²+ GPUs in 1 year or less. AMD's said it's serious, but Fiji on its own isn't convincing.
If AMD is, instead, going gung-ho on VR with a "GPU-per-eye" strategy, then erm, well, 400mm² would be easily enough in 2016. 8MP per eye isn't happening next year, sadly.
Frenetic Pony
Veteran
Not insofar as I know, both the FuryX and TitanX cap out thermally and are more or less the same size, which is the max 28nm size available. Meanwhile for power draw Nvidia obviously wins this last generation, but the 4xx series appears to be a new generation of chips while Pascal has some fiddling with memory bus and compute, but otherwise seems quite similar. So who knows how much of a gap that will be.
In fact looking at the DX12 benchmarks of say, the 2/390x vs the 980, and that the FuryX nearly keeps up with the 980ti/TitanX despite being a poorly balanced design overall, the advantage might go to AMD with another generation of improvement. But then really I'm just speculating without enough specifics.
As for static leakage, well gating can only take you so far unless you want to gate each piece of a chip individually. So better static control is certainly going to help, but you're probably right in questioning by how much.
Also, there's already 4k smartphones out and 8k phones planned soon! VR will happily take that technology for no development cost to them. F*in barmy I know, but once smartphone manufacturers latch onto an idea it seems impossible to let go. By 2020 we'll have 2mm thick 8k phones that will double as a good bread knife.
ImSpartacus
Regular
I'm pretty sure Pitcairn can't die at this point.
The Fury example showed possibly half a watt or more per degree C above 40C, on a Fury X with a water cooler and a temp ceiling that had dropped 30C below that of Hawaii. Extrapolating from 18W from a 25C swing in a 40C to 65C test to the 290X's 95C seems like an appreciable amount of power budget to play with, although it may be the case that HBM will constrain that upper range anyway.
Without more full power gating, the "off" transistors will have temperature and voltage components worsened by the most in-demand logic.
Besides that, FinFET has much better control at lower voltages, which benefits static and active. The foundries are comparing 14/16nm against 28nm, with the largest benefit being the roughly 2X improvement in power efficiency, since 20nm planar got most of the density improvement but very little power scaling.
Maxwell seems to be more responsive to voltage tweaks or just overclocking in general. The simplified scheduling probably means the pipeline has lower complexity in multiple stages, but I am not sure which element of the physical design could be different.
The transistor portion of the hybrid nodes is going to be significantly better than 28nm, whereas the wires are less so.
The GPU designs at the hybrid nodes should adapt to that reality, although it would be an interesting exercise to know how well the current architectures would fare if transplanted as-is. Maxwell seems generally more comfortable at 28nm than GCN, and sporadic tests by some sites seem to show less variation in power draw based on temp for some reason.
- Status
