Nano demonstrates that Fiji is substantially more hastened by clocks (hence voltage) than leakage power (though we can't isolate the leakage power component of the differences seen).
The lack of isolation is problematic, since we know that both elements get worse with voltage.
Finally, ~300W GPUs in an era where boost clock margins over base of as much as 20% would seem to imply that liquid cooling is here to stay.
There should be an ongoing market for that kind of cooling, but whichever architecture that requires it first to maintain parity with the competition is unlikely to be a winner.
If anything, Nano is proof that chips should be 600mm² before they are 10%+ higher in clocks.
Given the cost of the new processes, their earlier point in the maturation curve, and the likelihood that there is going to be a refresh (or two, or three) before 10nm, they may need to push for more performance per mm2 and consider Amdahl's Law for the portions of the GPU pipeline that do not reside in the CUs.
So the article is from the perspective of substantially higher clocks (let's say 50% higher 28nm -> 16nm?), which is not what GPUs are trying to do (though clearly NVidia pivots on a much higher base clock than AMD on the same node currently).
That's a notable difference, since FinFETs are very good at modest clocks, where their increased channel control and greater amount of channel per area footprint yield better leakage control and better transistor performance at lower voltage points. It significantly helped Intel apply its large cores to such a wide range of power bands. The large percentage of power budget coming from static leakage has been a long-time CPU rule of thumb, which Intel's process choices appear to have done quite a bit to rectify for the current and near-term geometries.
CPUs start to make tradeoffs for the higher range, where FinFET's benefits are more modest, but like you said it's not a range GPUs really dwell in. The trade-off that yields higher leakage for better switching speed in a design with a 2 GHz clock ceiling don't look like a promising choice for a GPU operating at half that.
My suspicion is that NVidia uses longer pipelines throughout the chip for all functional areas, which implies lower interconnectedness per cycle of unit processing. Which I'm guessing allows NVidia to use either a lower-power routing library or to bias their design more towards lower power consumption cells.
It's potentially lower-power, but seemingly capable of hitting higher voltages and clocks. Though it does lose a large amount of its power-efficiency when that happens, it doesn't need a liquid cooler and a VRM setup that apparently has to handle a significant number of >300W transients like Fury X apparently does.
Why Fury X seems on average to be less responsive to upping the voltage, while Maxwell seems to enjoy very nice overclocks, raises a question that was asked in the article about whether a design is limited by device switching speed or wire delay.
GPUs seem less likely to be hurt by switching delay, and a reduced level of interconnectedness can mean something like fewer long wires and reduced load on them relative to what the transistors can drive.
If transistors are sized for density and have heavier interconnect demands (more complexity, more distance to cover), they might top out at higher voltages before they can do enough to drive signals across units or the chip.
Nvidia has done things to reduce both complexity and distance with its latest GPUs. Some of AMD's choices like the amount of work done within 4 cycles might have traded complexity for more uniform compute performance.
I dunno, after all these years we still know practically nothing about the micro-architectural power-v-density and power-v-performance trade offs in GPUs. Almost everything we know about the progression through nodes and node technologies comes from CPU designs where the count of ALUs is substantially unchanged over the last decade (compared with GPUs) and idle power consumption has become more important, since custom blocks have been deployed for high-performance features (such as video decompression).
One of the data points for FinFET has been with Skylake's CPU and GPU power management, with duty cycling being used to keep things at a silicon-optimal clock and voltage point, where the cost of switching balances out against the increase in leakage with too-low voltage and clocks the design is not tuned for, particularly in a not-idle-enough range where the power cost of full power-gating's wakeup exceeds its savings.
That wasn't a tradeoff that would have paid off back when the static component of power consumption was a significant fraction of power budget, at least for complex CPUs with high peak clocks and a very wide dynamic range.
