AMD: Speculation, Rumors, and Discussion (Archive)

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Yes, but if Fury is 300 watts and AMD said that Polaris is 2 times perf/watt (Koduri said 2,5)

I went back and checked, Koduri never mentioned Fury as the card he was comparing against. The presentation that did mention Fury only said 2x.

The Polaris architecture was designed to bring VR to the masses.

Note that they used 390(non-X) as the VR to the masses benchmark. I expect all lower-end P10 models to hit that, and the highest-end ones to go maybe just a little over 390X. If they could do much better than that on a 232mm^2 chip, it would be the biggest win in GPUs since, well, ever.

Polaris 10 also demo'd running Hitman DX12 at greater than 60 FPS at 2560x1440 which is actually comparable or faster than Fury X.

This needs the usual disclaimer that they get to pick the most impressive benchmarks for the ones that they show to the press. The specific area of Hitman they were using had a lot of complex, tesselated, occluded geometry that Fury has to process before it can throw it away. It just so happens that one of the big architectural improvements of Polaris that they have mentioned is better and earlier discard of occluded geometry. I suspect that the specific scene was chosen precisely because it plays to the strengths of the card and shows it in the best possible light.
 
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Well here he's simply saying some of the Pascal cards will have 10GHz memory.. a couple of hours before last friday's announcement so way after the pics of GP104 with GDDR5X being leaked all over the internet.
Regardless, I'll take your word as him providing true information before.

I'm sure he was saying 10GHz on EVGA Precision which for nVidia OC demo at GTX 1080 unveil shown 5508MHz during demonstration (11GHz data rate). That means under LN2 conditions memory controller on these cards paired with the right chips will achieve 20GHz memory clocks.
 
The past few days a few rumors surfaced on the web, the GeForce GTX 1080 seems to be performing seriously good and as such AMD's board partners are in a bit of a fright. It seems only mainstream products will (likely) be launched in the Computex timeframe. Meaning there is no viable answer products wise in the higher-end to enthusiast segment to compete with Nvidia.

AMD was supposed to launch their high-end class VEGA (codename) product in early 2017, as it now seems that launch is being moved forward towards October. Realistically Nvidia isn't done, the 1080 will perform very nicely but they still have 'Big' Pascal GP100 on the shelves to answer any demand.

As the rumors goes (and they are just that) AMD decided to pull the launch of its next big silicon, Vega10 from early-2017 aunch not to October 2016. Vega10 will be the GPU that replaces the Hawaii/Grenada series. Vega should hold HBM2 memory and that's the culprit, it is just not available in volume.

"Vega10" is lined up to replace the 390/490 series. Vega11 will replace the FIJI Fury parts. Rumors right now indicate that Vega10 has 4096 stream processors and could compete with the GeForce GTX 1080 and GTX 1070. Vega11 would feature 6144 stream processors and would be lined against the GP100 big pascal GPU (think Titan).
http://www.guru3d.com/news-story/amd-vega-now-scheduled-for-october-launch.html
 
Wasn't this whole Vega pulled in to october tracked back to just another rumor or more like an opinion by a forum member? It's probably as reliable as Polaris pushed back to october.

And how likely would it be to just pull in Vega by a quarter when they can't even get Polaris out half a year after it was demoed.
 
People tend to mix up clock and data rates pretty wildly when it comes to memory.
And with GDDR5X it is even more of a fudge to most when considering actual and effective clocks, considering the clock speed is identical (at max spec) between quad and dual mode support for the 110 and 120 products; this is made more complicated with the 100 (10Gb/s memory) is rated to have a slightly higher clock speed in DDR over QDR mode, 1375 against 1250.
The difference is not the clocks (excluding what they do with the PLL inside the frame) but the Gbps/pin doubled for GDDR5X.
This is going by the operating frequency of the clocks in the Micron technical brief-spec.
CK_t,CK_c,Command,Address,WCK_t,WCK_c,EDC are identical in both modes, only the DQ and DBI_n double up in quad GDDR5X mode.

Cheers
 
If you check the official roadmap closely, center of the Vega square corresponds to end of november / beginning of december 2016. Launch at the end of october would be quite minor change (4-6 weeks, not a quarter).
 
If you check the official roadmap closely, center of the Vega square corresponds to end of november / beginning of december 2016. Launch at the end of october would be quite minor change (4-6 weeks, not a quarter).

That roadmap was later confirmed by AMD as early 2017 for Vega and not end of 2016.
 

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That roadmap was later confirmed by AMD as early 2017 for Vega and not end of 2016.
The only committed timeline of sorts I remember was Raja in an interview with PCPer March 2016 saying they would not be using HBM2 "until it is ready for mainstream", before that he said "doing new technology is exciting but expensive".
So they did not intend to use HBM2 until it was well supplied and costs had come down.

A very loose relational link of whose HBM2 they will use could be looked at in the context of the Pro Duo Fury.
How much work would it take to change this to HBM2?
If they had access to the Samsung HBM2 (personally I think NVIDIA is a priority client and taking much of the factory orders for the Tesla P100) that went into mass production end of January, why did they not use this in the Pro Duo where its cost could be taken into consideration?
Especially with the FirePro.

Part of it could be the technical logistics chain involved including the packaging, but more likely they cannot get hold of enough themselves or more likely they are in a partnership with SK Hynix for their product, which will not start to go into similar mass production until Q3 (will need ramping up just like Samsung did from January onwards).
Cheers
 
Wasn't this whole Vega pulled in to october tracked back to just another rumor or more like an opinion by a forum member? It's probably as reliable as Polaris pushed back to october.

And how likely would it be to just pull in Vega by a quarter when they can't even get Polaris out half a year after it was demoed.

Apparently. The tech report did a handy job of tracing the rumor back to it's supposed source on the s|a forums.

http://techreport.com/news/30113/rumor-amd-may-pull-vega-gpu-forward-for-an-october-launch

My apologies if this has already been posted. Always tricky to determine what has been posted where.
 
A very loose relational link of whose HBM2 they will use could be looked at in the context of the Pro Duo Fury.
How much work would it take to change this to HBM2?
A full new tapeout? As it stands, the Pro Duo is just using regular Fiji packages, no less, no more. Switching from HBM1 to HBM2 isn't just a matter of switching the HBM stacks (and correspondingly the interposer since the dimensions vary), but also requires a different memory controller.
 
A full new tapeout? As it stands, the Pro Duo is just using regular Fiji packages, no less, no more. Switching from HBM1 to HBM2 isn't just a matter of switching the HBM stacks (and correspondingly the interposer since the dimensions vary), but also requires a different memory controller.
Sure it would be a full tapeout of the Fiji GPU?
I cannot remember if both have similar pin architecture - around 1700 for HBM1 I think.
Yeah I appreciate aspects such as memory controller, but considering the market of the Pro Duo/FirePro this would make sense rather than limiting to 2x4GB, and the costs would cover this as it is more professional market than consumer.
Well that is if they had confidence it would sell.
Cheers
 
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A full new tapeout? As it stands, the Pro Duo is just using regular Fiji packages, no less, no more. Switching from HBM1 to HBM2 isn't just a matter of switching the HBM stacks (and correspondingly the interposer since the dimensions vary), but also requires a different memory controller.
While I agree wrt to the physical dimensions and it's implications to the interposer, I have a hard time remembering any largely functional difference from the JEDEC spec for HBM. Yes, for HBM gen2 running at full specified speed, you would probably re-optimize your controllers. But what else? Most things in HBM gen2 seem not to require much different controllers. Some options might, yes.
 
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