AMD: Speculation, Rumors, and Discussion (Archive)

This could also be a low end FireGl board for all we know.

 

It doesn't have to.

Fiji is the chip there with three different configurations, C880, C882 and C888. Fury, Nano and Fiji x2 respectively.

The supposedly polaris chips have been C9xx. The bigger one before this leak, C980 and C981, the latter the pricier one.

This otoh is C993 which might be a dual GPU solution but if it was a dual GPU solution with the above mentioned chip, it should've been C98x something.

 

Even though all Fijis were C88x, have you double checked that this applies to all the rest too? It could just aswell be a coincidence

 

Err... I'd love to point out that either there's one board that's on the low end (Polaris 10) that could, at max, be $250 in price. Leaving, if this were a dual high end GPU, a single GPU of it to be $900+

So either there's 3 boards, or there's no middle board at all with a huge gap, and that shipping earlier of a board worth $390 or whatever it was is totally false. And I've found no other mention of "2 GPUs in 2016" at all except the Forbes article. Just because you see it multiple times doesn't mean it's not just being re-spread from the same single source. Another explanation for the "2 GPUs in 2016" is that it specifically mentions "2 14nm Finfet GPUs" and Anandtech already stated AMD is using both 14nm Samsung/GloFlo finfet and TSMC's 16nm Finfet. Could well be there's a third GPU on TSMCs process.

 

AFAIK TSMC is still more or less speculation - I mean, yes, they said they'll use TSMC too, but it's been silence on it since then, and even then they never mentioned specifically GPUs in the context, could just as well be APUs for example.

And no, I'm not referring to just reading about 2 GPUs from different sources all based on Forbes via one or more via, but that they've mentioned it on other occasions too.

 

For example…?

 

At least Sonoma if I'm not mistaken

 

Hello, i'm new here.

Is AMD's statement, which says that GCN in Maximum can have 4 shader arrays each with 16 CUs and 4 ROP-Blocks, still valid ?

If yes, wich Parts can be overhauled without violating this rule, but giving that extra performance for the Top-Chip on 14-16nm?

Are the Parts AMD showed as *NEW* in its Polaris Presentation the right addresses ? Maybe they doubble from 64 to 128 ALUs in one CU and upgrading the Scalar-Unit and the Addressing-Units.​

 

AMD can do what it wants with its own architecture. The statements relating to the limits of the current products were in the context that AMD decided against making those changes for the revisions that have been made so far.

Polaris is being touted as being a significant change, which means they could have changed some of those parameters. The details are not available, to my knowledge.

 

I believe the article that most people reference is a venturebeat interview with koduri. I'm almost positive that it's been posted before, but I think it would be helpful to post it again.

http://venturebeat.com/2016/01/15/a...graphics-immersion-with-16k-screens/view-all/

Koduri states it pretty plainly and unambiguously:

Some people have said that the third gpu isn't under the Polaris banner. However, he clearly says, "We have two versions of these FinFET GPUs."

That phrase, along with him plainly using the Polaris 10 and Polaris 11 codename really brings credibility to the idea of amd only having two new GPUs in 2016.

There are never guarantees on this world, but I think his wording allows a certain amount of confidence. Thoughts?

 

One thing about that portion of the interview is that it stems from the last part of the earlier answer concerning AMD's goal of bringing console-level performance to a thin and light notebook. It might be construed that the question and answer that were quoted were within the context of that earlier statement.

That's not to say that the two GPUs mentioned couldn't be AMD's 2016 offerings, just that the statements leave some interpretive room.

 

Maybe they didn't have the 3rd GPU at that time. Look at the dates of shipping (Zauba). The interview was published 2-3 weeks before the first shipping of the most expensive board.

 

Too many ways to interrupt what was stated (if we take things out of context of what was stated), and adding in Zumba findings which frankly don't match up with anything to the $ amount because of import tax amounts,conversion rates, and insured rates don't point to anything. Too many ifs, ands, and buts.

 

So tempted

 

https://www.linkedin.com/in/jurgen-hao-8483a768

Sounds like Polaris 11. Hawaii is 438mm2 with 44 CUs, so 232mm2 for a finfet part could be the rumored 48 CU GPU that will replace the Radeon 290/390.

 

I wonder if 430 blocks describes just the logic area of the chip, which may not be the die size. The GDDR5 PHY, for example, may not count.

Regardless, when talking about scaling Hawaii there are a number of factors:

1. all PHYs tend not to scale just because of a change in process. So the logic takes up less of the die, so a process change will save less die space than expected
   
2. Hawaii doesn't have all the extra stuff that's in Tonga. Remember Tonga spent a vast number of transistors apparently doing practically nothing (slight gain from colour compression, lots of changes to ALUs, other stuff that practically no one uses)
3. the large Polaris chip probably only has a 256-bit interface, which is a substantial saving in die area

 

That 430 is the number of partitions in the floor plan. The tools aren't able to manage the full design in one go, so it gets split up in a quilt of smaller blocks that are placed and routed individually.
But this introduces the need to manage wires that go between blocks or busses that simply travers the blocks, which requires pin placement, feed-through and repeater insertion. That's what this guy was doing.

It's impossible to say how the number of blocks relates to functional units. Inside a single CU, there could be multiple blocks. They could even use different P&R tools for different blocks: some for data path placement, another for more random logic. etc.

 

BTW: I'm anything but litigious, but if I were AMD, I'd sue the hell out of that guy for leaking trade secrets. This is really outrageous.

 

I agree, odd to show things like that on a resume too, its not like a potential hiring company would ask such questions about IP of particular products too kind of has no place on a resume.

 

Yeah, the die size in particular is hard to defend.