Ah ok. It looked plausible enough
(Just because it looks like it should be possible to fit 16 tris into a wave doesn't mean the hw really can do it...). In any case, with 16 tris per wave that means you may need 24kB of LDS just for attributes in the worst case (per wave).
I hope it's the former, because the latter, I'm still not entirely convinced of being a hardware solution (as in dedicated logic) rather than GeometryFX-like driver injection.
TBH more and more, because more and more cases have either windows or even full glass sidepanels. (I myself don't have either one, though I think (without checking under the desk) that my sidepanel does have grille for a fan
Just knowing that a graphics card has LEDs improves framerates and rendering quality.
May be worth withholding judgment until we see the architecture. Fast scalar processors and the potential ability to regroup waves, while sort of a software solution, would seem to change some of those dynamics significantly. A software solution in that case may be a far more flexible option and maintain performance. The culling process could be occurring in stages as well. Seems likely Nvidia will be doing something similar with Volta, as there are a lot of papers about scalars floating about for both architectures.
NVidia also has a fair few papers regarding Temporal SIMT (including patents), aligned with several independent engineers and with Bill Dally talking about that maybe 2018 relating to their Tesla architecture.
And I want the heat exhausted out the back because I run my computer semi-passively. There's just one 120 mm silent fan that rarely turns on servicing the entire computer (no CPU fan) with a hybrid PSU that usually runs without activating its fan.
http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf
Then the reference 480(X) should be pretty ideal. Its design seem a remarked improvement compared to previous AMD designs, putting power delivery at the back of the PCB instead of up front made the PCB shorter and gave the blower the ability to suck air from both sides of the card. It's disappointing though that AMD chose to gimp power delivery so much with just a single auxiliary six-pin power connector, with such a smart cooler design and all.
Well Nvidia went that route of LIW publically back in 2011 as shown with the paper linked.I read it but it doesn't really say how each lane can fetch and decode independent instructions. If each lane can fetch a different instruction that's 8X more ICACHE BW!
Perhaps there is a clever solution for this but to me it sounds like you got to have N scalar cores that share a bunch of other logic to amortize their cost. Temporal SIMT sounds better than 'super dumb LIW cores that share some resources'
They were still talking about it last year as a requirement for eliminating waste/redundancy and improving efficiency, all of which are critical when looking to evolve more towards an exascale capable Tesla GPU.
