All ready!
AMD: Southern Islands (7*** series) Speculation/ Rumour Thread
- Thread starter UniversalTruth
- Start date
iMacmatician
Regular
Interesting new info from SemiAccurate:
http://semiaccurate.com/2011/11/17/more-bits-on-hd7000northern-islandsgcn-leak/
http://semiaccurate.com/2011/11/17/more-bits-on-hd7000northern-islandsgcn-leak/
I detect sarcasm in that update. I'm not sure if there's a reason for that. AMD needs bandwidth, and if the rumor is accurate the best way to that was widening the bus.
By extension, the board is going to be 1.5 or 3 gigs.
The number of memory channels at that width does mean 50% more L2, but unless AMD was able to really compress the size of its IO the chip will need to be bigger to have the room for the wider bus.
By extension, the board is going to be 1.5 or 3 gigs.
The number of memory channels at that width does mean 50% more L2, but unless AMD was able to really compress the size of its IO the chip will need to be bigger to have the room for the wider bus.
My going assumption until proven otherwise is that GCN would be that architecture.
There could be other reasons to have a wider bus, like if there are cost savings to reverting to slower speed grades of GDDR5, but I think having larger bandwidth demands would be a strong reason to have a wider bus.
There could be other reasons to have a wider bus, like if there are cost savings to reverting to slower speed grades of GDDR5, but I think having larger bandwidth demands would be a strong reason to have a wider bus.
There are a number of instances where OpenCl projects hit the bandwidth barrier first, so it could be a GPGPU concession.
There are also instances in games where bandwidth does limit performance, if only for a portion of the run-time. More bandwidth could be a move to raise minimum FPS in scenes that are otherwise high.
There are also instances in games where bandwidth does limit performance, if only for a portion of the run-time. More bandwidth could be a move to raise minimum FPS in scenes that are otherwise high.
It's hard to have a wider bus on a small die.
The architecture is probably less dense, so the larger die may also be needed to keep the CU count high enough to give AMD a decent increase in peak FLOPs.
The architecture is probably less dense, so the larger die may also be needed to keep the CU count high enough to give AMD a decent increase in peak FLOPs.
One of the interviews from back around AFDS made it sound like GCN's units wouldn't be that much larger than Cayman's but they didn't mention about any of the other parts of the chip.
Hmm, RV670 was 192mm² and featured a 256-bit bus on 55nm. Could they really have so much trouble fitting a 384-bit bus on a ~3XXmm² die on 28nm?
The picture of RV770 showed there wasn't enough room for another 128 bits of GDDR5 on the perimeter of a 256 mm2 die.
Also RV670 was GDDR3/4 compatiable.
Heck, they fit a 512bit bus on R600 which was what? ~420mm2?
I've also heard it's 384-bit so I'm very inclined to believe this.
I have no information on this part but I wouldn't be surprised if NVIDIA went for 512-bit in the ultra-high-end this time. And I don't expect them to screw up as badly as GT200 again so I doubt AMD could get away with a small 256-bit die anyway.
I'm not seeing much evidence that AMD is (noticeably) less bandwidth efficient than NVIDIA - or are you saying further improvements would be more beneficial than a brute force increase in bus width? I agree that'd be nice but I'm honestly not sure how much of an improvement you could still get without a massive change in rendering architecture. Or are you maybe suggesting an increase in the ALU:TEX ratio?
I have no information on this part but I wouldn't be surprised if NVIDIA went for 512-bit in the ultra-high-end this time. And I don't expect them to screw up as badly as GT200 again so I doubt AMD could get away with a small 256-bit die anyway.
AMD looks less efficient to me there. GTX 460 for instance wasn't dependent that much on bandwidth, even losing a quarter of it had not that much of an impact. GTX 560Ti also has quite a bit less bandwidth than HD 6950 for instance and IIRC it doesn't really get that much more performance if you overclock the memory. Or with low end parts, the no bandwidth part GT520 manages to beat the HD6450 by quite some margin if the latter has equally low bandwidth when equipped with ddr3.
That said with 256bit gddr5 it would be impossible to have more bandwidth than the GTX 580, and since the top end HD7000 part should be quite a bit faster indeed a wider gddr5 interface is probably needed even if bandwidth efficiency is improved.
iMacmatician
Regular
Do you think it's more or less likely that high-end Kepler will have a 512-bit bus over a 384-bit bus? (The latter is my "default" assumption, but I wouldn't be that surprised if they went 512-bit.) I'm asking because GF100/GF110's memory speeds are significantly lower than Cypress/Cayman's, and so NVIDIA would have more room for bandwidth increases without needing a wider bus or going to XDR2 (unless they have other issues). Even 256-bit at 6 GHz (IIRC the rated speed of 6970's memory) would match the 580's bandwidth (but I highly doubt they would go that route unless the high-end Kepler is GF114-sized or so, and even then…).
Similar threads
