AMD: Sea Islands R1100 (8*** series) Speculation/ Rumour Thread

[Albuquerque]

AMD would rather go through a multimillion dollar tapeout and product ramp at a bad time in the development cycle, just so some people on web forums that wouldn't by the OEM cards will like the company better?

Yes, that's exactly what we want.

We also want lower taxes, more handouts, more guns, less oversight, more technology, less price, less stuff made in china, more stuff made in america, the best quality without cutting corners, every feature to be available on every part, and we want ALL of this last year which means it's already too late and the damage is done and I'll never buy it ever again and nobody else will and everyone will hate it and nobody will like it and it's a low down dirty trick and it's a shame and it's a spit-in-the-face of democracy and life and happiness and it will kill puppies and the underdog will always lose.

</webforumcliquemob>

Am I doing it right?

 

[3dilettante]

That's not say that I don't find the rebrands depressing, just not something I'd consider worth getting angry about.
I'd find it scuzzier if AMD used the rebrand to reset its price structure so that it could sell a 7970 at the same prices it had when it first introduced the product.

Unfortunately, more time seems to be elapsing between notable changes, which makes things significantly less interesting.

 

[silent_guy]

That's not say that I don't find the rebrands depressing, just not something I'd consider worth getting angry about.

Well, somebody finally said it. Thank you.
OEM probably asked for it. AMD delivered. Good for them. They should do anything they can to extract as much money as possible.

 

[Homeles]

I don't see who one excludes the other? You can have the crossbar and still have 48 ROPs.

What would be the point of that? The point of the 4x8 ROP/6x64 bit bus configuration is to provide the bandwidth-hungry ROPs with more cache and bandwdith, without having to add more ROPs as per traditional GPU design. Add more ROPs, and not only does the crossbar become redundant, but the ROPs are less efficient.

 

[silent_guy]

What would be the point of that? The point of the 4x8 ROP/6x64 bit bus configuration is to provide the bandwidth-hungry ROPs with more cache and bandwdith, without having to add more ROPs as per traditional GPU design. Add more ROPs, and not only does the crossbar become redundant, but the ROPs are less efficient.

You're speculating that the goal is to provide more BW per ROP. I never thought of it that way, and it's definitely possible. But it's also possible that they didn't want to spend the area on a 6x8 ROP configuration to save area.

Now with 6x8 a crossbar may not make as much sense if you have a full configuration, but maybe it does if you have units disabled for lower performance versions. Or it may also be a matter of having an easy parametrizable design that can be quickly turned around into different silicon configurations/smaller chips. Etc.

Who knows...

 

[lanek]

I have never buy a hardware component from OEM ( or maybe yes my first Atari 1040st ) ( even for laptop if someone ask, i dont use oem brand like Apple, dell, or HP or lenovo, i contract a shop for use the componenent i want for do my laptop ) .....

So it dont disturb me to see this for OEM ( who ask anyway and if you want treat with them you need do this type of contract ).


But i still say, marekting wise its a bad thing... Its not good for the image of AMD...... And they really need to have a good image .

( Not related but ,,,,, )
Now lets be honest, GCN on the paper is one or the best gpu architecture never released, and somewhere, outside software use ( CUDA ), certainly the most powerfull computing architecture never released .
( even the GK110 is not so much able 1 year after this release, to push down GCN.... ... with only some few optimisations this architecture could pull down easely the Nvidia counter part who is the GK110 or actually the K20x ( again without taking in account the cuda implementation who is wide used )

 

[Homeles]

You're speculating that the goal is to provide more BW per ROP. I never thought of it that way, and it's definitely possible. But it's also possible that they didn't want to spend the area on a 6x8 ROP configuration to save area.

Now with 6x8 a crossbar may not make as much sense if you have a full configuration, but maybe it does if you have units disabled for lower performance versions. Or it may also be a matter of having an easy parametrizable design that can be quickly turned around into different silicon configurations/smaller chips. Etc.

Who knows...

I'm not speculating. I'm making a claim.

AnandTech's 7970 review from Ryan Smith is the source of that claim.
www.anandtech.com/show/5261/amd-radeon-hd-7970-review/4

But you do bring up interesting points.

 

[silent_guy]

I'm not speculating. I'm making a claim.

Well, excuse me for not re-reading all the 7970 reviews out there.

It may well be true that ROPs can't be fed (or unload) data fast enough, but I'm not outright willing to accept this as being 100% true: if I were a marketing guy, it'd be the kind of explanation I'd use to justify an unexpected shortfall of units.

(Now don't laugh with the calculations I'm doing below: this is a very layman's analysis. So, please, please, correct any dumb mistake I'm making below, I'm trying to learn here!)

If we ignore the L2 cache (which is going to have a higher BW than an MC, otherwise what's the point?), then the max 24bit pixel bandwidth per MC will be: 6e9*64/24=16G pixels/s. If you have 8 ROPs per MC, that's 2G pixels/s/ROP. I assume that the max ROP throughout is spec'ed for this most common case, so a single ROP handles 1 pixel per clock. The 7970 runs at 1GHz, so the MC has double the bandwidth needed for a single ROP doing the most basic fill operation. This is arguably the case with the lowest BW needs. Z read + Z write + RGB write is the more common case, but with an L2 and Z compression, I just don't see how additional ROPs won't be a performance benefit.

Don't get me wrong: I'm not saying that 32 ROPs was fundamentally incorrect. It's just that it was a kind trade-off that's made by the truck load in any complex engineering project.

 

[RedVi]

How is it a trade off? Normalizing the clock speeds gives 7970 a pixel fillrate 15% higher than GTX580 despite having 33% fewer ROPs.

 

[Silent_Buddha]

How is it a trade off? Normalizing the clock speeds gives 7970 a pixel fillrate 15% higher than GTX580 despite having 33% fewer ROPs.

I think he means it's sort of a trade off in that if the sky is the limit, then more of them could likely provide more performance.

The reality, however, is that the sky isn't the limit. There's design and process constraints. So it's a tradeoff. Or perhaps a better phrase is that the balance of performance from various area's of the chip worked out better with 32 ROPs and more of something somewhere else. Rather than more ROPs and less of something elsewhere.

Regards,
SB

 

[silent_guy]

The reality, however, is that the sky isn't the limit. There's design and process constraints. So it's a tradeoff. Or perhaps a better phrase is that the balance of performance from various area's of the chip worked out better with 32 ROPs and more of something somewhere else. Rather than more ROPs and less of something elsewhere.

Yes, e.g. for a specific target silicon area. If the area budget goes up a little, it may make sense to up the number of ROPs more proportionally than, say, the number of shaders.

 

[Alexko]

I have never buy a hardware component from OEM ( or maybe yes my first Atari 1040st ) ( even for laptop if someone ask, i dont use oem brand like Apple, dell, or HP or lenovo, i contract a shop for use the componenent i want for do my laptop ) .....

So it dont disturb me to see this for OEM ( who ask anyway and if you want treat with them you need do this type of contract ).


But i still say, marekting wise its a bad thing... Its not good for the image of AMD...... And they really need to have a good image .

OEM only products have a tendency to end up on the retail market anyway.

 

[seahawk]

And a OEM would not be too happy if they launch a new line-up featring the mighty 8***, if AMD launches new retail 9*** shortly after. This rebranding only makes sense, when the real refresh is either cancelled or not out before 3Q13.

 

[Alexko]

And a OEM would not be too happy if they launch a new line-up featring the mighty 8***, if AMD launches new retail 9*** shortly after. This rebranding only makes sense, when the real refresh is either cancelled or not out before 3Q13.

AMD released its graphics roadmap just a few days ago, the refresh is clearly neither canceled nor delayed to Q3:

 

[DmitryKo]

Well, looks like that [post=1691767]HD 8880 part rumored for the next Xbox[/post] is a real product which should be based on GCN2, as opposed to OEM products like HD 8870...

 

[AlexV]

Hmm, I suggest people take a peek at how the GPUs in Richland and Kabini will be branded, before considering mystical custom GPUs for XBOXNext...

 

[seahawk]

AMD released its graphics roadmap just a few days ago, the refresh is clearly neither canceled nor delayed to Q3:

I am aware of this. Yet it makes the rebranding even stranger. If it would have been just the mobile chips, well ok. But they also went with Tahiti and Pitcairn top dogs. The new line has one obvious opening for Oland, but that is about it.

So going by the road map the longest shelf life of those rebrands would be 4 months. But it would alos mean that the refresh will launch as 9XX0.

The only good reason I can imagine is a way to skip the 8X00 designation (due to being closely linked to the GeForce series) and go for the 9X00 (closely linked to R300) asap. But then they end up with a system that would suggest a 2 generation jumo from 7 to 9, with a refresh made on the same process. Not that good either.

 

[UniversalTruth]

The quality of the slide...
What is this fashion to put intervals right after words before dаshes (or commas) and no interval after that?

 

[Homeles]

Well, looks like that [post=1691767]HD 8880 part rumored for the next Xbox[/post] is a real product which should be based on GCN2, as opposed to OEM products like HD 8870...

If this is true, the next XBOX is going to quite expensive in relation to its competition. Powerful, yes, but also costly.

Don't get me wrong: I'm not saying that 32 ROPs was fundamentally incorrect. It's just that it was a kind trade-off that's made by the truck load in any complex engineering project.

Right. I agree that there would be additional benefit from going to 48 ROPs -- architectural design is a massive game of diminishing returns -- but they way I understand it is that it would negate their decision to go asymmetrical. If the point really was to feed the ROPs with more bandwidth, going to 48 ROPs while keeping a 384 bit bus would be a reversion to their older philosophy.

I wonder if AMD or Nvidia will ever hit the holy grail of having a 7 Gbps bus. I was rather surprised by Nvidia's accomplishment of being the first of the two to hit 6 Gbps, considering the historical precedent. It seems to be increasingly difficult to bump speeds higher, but it would be a great thing for them to achieve; provided that it wasn't too resource intensive, of course.

 

[CarstenS]

I'm not speculating. I'm making a claim.

AnandTech's 7970 review from Ryan Smith is the source of that claim.
www.anandtech.com/show/5261/amd-radeon-hd-7970-review/4

But you do bring up interesting points.

I'm not so sure about the ROP problems Ryan mentions*. In directed tests, efficiency wrt to pixels is fine at least since the first DX11 generation (fine being 98% or greater). Z-efficiency was significantly lower, this was remedied (from 68 to 81/82 %) by the new ROPs in Cayman (but not Barts), which got largely carried over to SI.

The pixel fill in 3DMark traditionally measures memory bandwidth as a whole given roughly comparable architectures (single-cycle FP16 for example).


edit:
* I've heard the story of Cayman and earlier hitting 27-28 ppc only, whereas Tahiti would frequently go up to 32 as well. But I felt the emphasis was on setup-problems and wavefront creation on the VLIW-parts and not the ROPs being the culprits.