It was obvious because AMD simply couldn't keep using Bulldozer as a base since it's too hopeless an architecture (AMD lost the laptop and server markets because of Bulldozer).
Regarding the 52% improvement, it's easier to get such gains when your previous baseline was poor to begin with.
VIA's baseline is the Nano CPU. If you give VIA similar resources as AMD/Intel and convince them to go for it, then you can bet that their next CPU would be 300% faster than Nano, but that doesn't mean they would keep getting similar gains generation after generation. IMO, AMD's future performance gains will be more similar to Intel's.
And Zen is very efficient up to the 3GHz range but change it to 4GHz and its efficiency drops dramatically, meanwhile Intel can reach higher clockrates. I think Ryzen is a very nice CPU that will bring competition back to the x86 arena, but right now Intel isn't in a desperate situation at all. They could increase clockrates a bit, put two more cores on their desktop CPUs and drop prices a bit, that would be enough.
But who knows what's going to happen. We're mostly speculating, so let's wait and see what the future brings.
No problem, no offense taken. I hope your mother gets better quickly.
I see one possible quick 'fix' for inter-CCX and memory latency - increase InfinityFabric clock from 1/2 of mem to 1:1 ratio. Even current silicon supports it in Debug mode, but question remains, how it affects power and max frequency CPU can run at.
It could also be a question of whether or not something blows up. Something that crosses so many functional blocks and clock regions could have timing issues that prompted them to back off. One item to note is that the 1:1 ratio is between the fabric and the DDR clock, not the IMC. Going to 1:1 actually creates a mismatch with the controller itself. It appears to be a straightforward ratio to maintain, but still tightens margin for error or potentially adds a ceiling to the DRAM clock if the uncore cannot match it.
I saw a link on Ars technica concerning the fabric width:
https://www.reddit.com/r/Amd/comments/5zr8lv/i_asked_amd_a_followup_question_about_infinity/
This is a 256-bit bidirectional crossbar. The inter-CCX bandwidth numbers given earlier don't act like it's 256 bits of bandwidth per clock in each direction, however.
hoom
Veteran
Well since it doesn't appear to be suffering in TDP there is probably not much down side to a 2* CCX quad, plus you get 4MB L3/core.
I presume they can push out a native quad core if sales go mental? Or salvage from the APU I guess.
itsmydamnation
Veteran
There is supposed to be a big mirco code update in may that should have a big impact in terms of memory compatibility and max DDR clock, so who knows what flexibility that would/might bring in the dividers/fabric.
Jawed
Legend
I was thinking perhaps that 8 CCXs would be the nodes on a cube and the bandwidth per CCX would be pre-allocated into three equal amounts for the 3 edges to "nearest" nodes on the cube plus the final quarter of the bandwidth would be for "local" stuff. So bandwidth between a single pair of CCXs would be one quarter of the bandwidth that a CCX could use in an 8 CCX config.
But I haven't studied CCX link architecture, so it was just an idle question more than anything.
Jawed
Legend
I noticed just now that when I look at W10's CPU section in Task Manager under the Performance tab, that the graph has three options when you right-click it and look at the "Change graph to" sub-menu:
- Overall utilisation
- Logical processors
- NUMA nodes
Sam from CanardPC says there are HEDT samples of Ryzen with 16 cores and 32 threads floating around, with clock speeds around 2.4GHz and 2.8GHz (respectively base and Turbo, I would assume), about 150W, 4 memory channels, launch scheduled within 4~6 months: https://twitter.com/CPCHardware/status/843099198799187968
It doesn't, the option is greyed out on my 1700.
Decisions, decisions! Should I buy Ryzen AM4 now or wait for SR3r2 and jump straight to 32T CPU ...
AMD will have a really busy summer it seems! Between VEGA soonTM and R5 in the 1H'17 they also need to launch R3, Naples and HEDT platform in 2H'17 not forgetting about launching RX5xx refresh and APU's this year!
Finally some interesting times ahead
AMD will have a really busy summer it seems! Between VEGA soonTM and R5 in the 1H'17 they also need to launch R3, Naples and HEDT platform in 2H'17 not forgetting about launching RX5xx refresh and APU's this year!
Finally some interesting times ahead
The HEDT samples have pretty low Turbo clocks, although I'm not entirely certain why. Perhaps they're made up of low-leakage dies that can't clock very high, because otherwise, with a 150W TDP, you'd expect a single core to be able to reach 4.0GHz without too much trouble.
Anarchist4000
Veteran
Infinity is a mesh, so that was my assumption as well. Link approaches/exceeds L3 bandwidth as nodes/links are added. AMD mentioned routing around congested links though. These results would imply links can't be bonded together as the nodes should scale to 4-8 CCXs or more for APUs. So what limits the links, protocol?
ES samples, they are in the wild for testing purpose, final clock could be quite different.
It is possible too that the turbo maintain more cores at high clock.
Personally for this type CPU, i strictly dont care about a turbo mode who run on "1-2 cores" at maximum speed, i want a sustained speed on a maximum of them.
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