AMD RyZen CPU Architecture for 2017

Well if it is fake, it's the best road map fake I ever seen. The type face looks about right, the color scheme is right, the layout is done by someone who clearly knows where to put them pixels.
Apart from that, the specs looks believable, but hey, maybe it's just a wish list :)
 
I am not a German speaker, so I cannot parse the auto-translation's choice for "völlig falsch", as the web resources show falsch coming up for both counterfeit and incorrect.
It's also not clear from auto-translate if specific or all the slides were "falsch".

Roadmap aside, (too optimistic to be real?) I googled some of AMD's slides for other cores, and a few things seemed to have a pattern.
Orange is not a common color for CPU core box diagrams, but I think there may have been an exception I lost track of in my search. It is used for the blocks representing Kaveri's GPU.
When outlining core information, AMD normally has a vertical list to the side or vertical column(s) below.
It was rare to find diagonally oriented text, and not below a core or SOC representation. Even when text was listed on a diagonal, the ones I found did not sweep left from top to bottom, rather reading from the top would lead the reader's eye on a forward course.
Sometimes, the background color fill would sweep or have diagonals in the other direction, but the text would not do the same.
The box core representations given by AMD also make a habit of showing the code name in quotes at the top in mixed case, which the rumor slide did not do.
The right-triangle caret or any large caret tends to be used to point out a larger claim regarding a design outcome or high-level characterization, like X% improvement or New features for X domain. The particulars, like how many cores or what widgets go into it tend to go in sub-items below with lesser bulletpoints.
That would be stylistically different but only incorrect if the style sheet the technical writers/marketers would be using has not been changed.

That the technical details seem "believable" is probably helped because only a few things were actually claimed. It doesn't help that AMD has resorted to such milquetoast presentation practices in the past, but that's more AMD's problem for weaseling out slides so vague that they can safely be right from so many contradictory points of view (ex. Bulldozer's pipelines).
 
That the technical details seem "believable" is probably helped because only a few things were actually claimed. It doesn't help that AMD has resorted to such milquetoast presentation practices in the past, but that's more AMD's problem for weaseling out slides so vague that they can safely be right from so many contradictory points of view (ex. Bulldozer's pipelines).

Vague? AMD? You must be thinking of some other company.






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Anyway, only three more days to wait now.
 
I really hope that the cache performance/technical quality has been improved significantly in this.
It seems to have been a pretty big issue that hasn't been addressed in BD/late Phenom.

I'm probably going to be upgrading next year & I'd love to be able to reasonably buy AMD not Intel.
 
I'll be upgrading my system late next year also, I'd love to be able to go for an 8 core machine without paying through the nose for it and while still having decent single core IPC and perf/watt. I haven't been with AMD since an A64 3500+, I really hope they can deliver after the lacklustre bulldozer range. I hope May 6 reveals some sort of promising info.
 
Zen would have to be pretty bad not to be way better than Bulldozer since BD was the exact opposite of everything you should do if you want to make a good CPU. I'm still waiting for AMD's bulldozer punchline and now starting to think they may have been serious about the whole thing. Or maybe the punchline was the 200+W 9550?
 
I didn't catch that part of AMD's Analyst Day, but Hardware.Fr reports that AMD said something about Zen-based Opterons offering disruptive memory bandwidth:
AMD lancera également des puces Zen sous la forme d'Opteron pour les plateformes serveurs haute performances où le constructeur évoque une « bande passante mémoire disruptive » qui peut laisser penser que le constructeur pourrait, pour certaines versions serveurs, proposer quelque chose d'original – pourquoi pas de la mémoire HBM.
http://www.hardware.fr/news/14202/zen-socket-am4-hbm-amd-parle-avenir.html

This may well mean HBM, perhaps as a cache rather than a replacement to DDR3/4, because that would probably be too expensive and too restrictive in terms of capacity.

But it could just be silly PR talk for quad-channel DDR4 or something.
 
I'll be upgrading my system late next year also, I'd love to be able to go for an 8 core machine without paying through the nose for it and while still having decent single core IPC and perf/watt. I haven't been with AMD since an A64 3500+, I really hope they can deliver after the lacklustre bulldozer range. I hope May 6 reveals some sort of promising info.
if they can get close to 15% ipc performance of whatever intels chip is at reasonable wattage for a lower cost I wouldn't mind jumping on another amd platform. But that's a huge hole they have to climb out of
 
But it could just be silly PR talk for quad-channel DDR4 or something.

By 2016, Intel will have been selling a quad-channel DDR4 platform (LGA2011-3) for a year or more.
To call that disruptive seems like a bit of an exaggeration.
 
By 2016, Intel will have been selling a quad-channel DDR4 platform (LGA2011-3) for a year or more.
To call that disruptive seems like a bit of an exaggeration.

Isn't that the very definition of marketing? :D

But I sure hope there's more to it than that.
 
aren't they going from 32nm with the latest bulldozers to 14nm finfet ? I would thik that would be the biggest gain. Intel has done more than 40% since their 32nm chips which was what nehlam ?
According to Wikipedia, Steamroller and the upcoming Excavator is on 28nm.
 
aren't they going from 32nm with the latest bulldozers to 14nm finfet ? I would thik that would be the biggest gain
Well smaller transistors doesn't on its own make an IPC improvement.
If you make exactly the same logic in 32nm and in 14nm finfet its still going to have the same IPC.
 
Well smaller transistors doesn't on its own make an IPC improvement.
If you make exactly the same logic in 32nm and in 14nm finfet its still going to have the same IPC.

true but it will certainly help clocks and power usage and allow them to fit more transitors in
 
Isn't that the very definition of marketing? :D

But I sure hope there's more to it than that.
You know, Fuad claimed eight DDR4 channels with his... 32-core Opteron rumour. This would really be "disruptive", since the single-socket record holder (?) so far is Knights Landing with six in the x86 space IRRC...
 
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