This seems like a good thing, previously L3 was at Northbridge clocks wasn't it?
It could reduce the synchronization penalties from crossing disparate domains, although the slower cores would be out of step. It might be that this keeps the L2's shadow tags from bottlenecking cores if they were kept at a slower uncore clock.
Power-wise, or perhaps for clock scaling/turbo, it's something extra that needs to be driven harder when single-core performance is being pushed.
Also something that has bugged me: AMD talks about 'same average latency' to all L3 slices.
On average, accesses should fall into an even distribution among the 4 L3 slices and their portion of the shadow tags.
It might take a specific pattern to really hit a local slice, and there's probably some pipelining that might constrain how frequently a core can draw from a given quadrant. A 32 byte connection for one thing is going to eat up an extra cycle of access time, so that's an extra cycle that's going to serve as a bit of margin that can allow a pipeline to overlap some of the remote vs local latency. Other elements like the serial nature of the shadow tag checks, array access, and contention may also have fixed costs that mean the variable portion's influence is diluted.
Shouldn't that be done/started before the lunch?
Kind of chicken and the egg to devs to find issues for a chip and platform that has only relatively recently been made available, and some of the timelines may be shorter than otherwise because of early samples.
The platform seems pretty raw as it is, but the alternative would be to delay it even further. A lot of issues wouldn't be found until after that anyway.
I was hoping that there would be more disclosure about the neural net prediction for core execution, but that slide didn't show up in the reviews I've seen so far.
The chip seems a bit raw, some things look kind of inflexible. It's still decently close in many areas to a very mature platform and chip, and there is only so much that can compensate for that.
The silicon does look like it's being pushed pretty heavily already, thanks to the performance features in place.
I think part of the reason why there's no 140W SKU is that it doesn't seem like the cores and CCXs are really scoped to scale speeds and voltages much more than they do. It's sort of a "balance" thing where there's less left bottlenecked by having the cores lose area or power efficiency by having margin in out of spec scenarios. Perhaps that's a question of physical maturity, or if you want 30% more power draw it would take another CCX to do it.
I am curious now what import this has for the APUs, if the CPU-only physical implementation reaches these speeds. The GPU might not make it easier.
Ryzen seems decent enough, being usually in the area of some good cores. It's a bit of a lateral move for many gamers, unfortunately.
It's early days, and perhaps people have forgotten about the CPU optimization game being so important since the BD line was so terrible for so long that it was pointless.
I wouldn't have minded some kind of value-add or "wait, there's more" for the architecture to keep things interesting. It's a pretty standard and mostly respectable product with a decent value proposition if you don't already have something that performs similarly. There seems to be more waiting in the wings for the non-consumer market.
