AMD RyZen CPU Architecture for 2017

[Alexko]

I agree, its long past time that 8 cores became the high end and quad the baseline IMO. Unfortunately everything I've seen points to skylake being the same as previous gens with regards to core count.

From a technical point of view, that would make a lot of sense for desktops, but not so much for laptops.

The business side is the problem. If Intel had to make chips with 2, 4, 8 cores, and scaled graphics EUs by as many levels, that would mean quite a lot of chips (up to 9, if every combination were implemented). I'm not sure Intel wants to bother with that; and I'm sure they don't want to eat into the Xeon market. They'll do it if AMD comes out with a really good 8-core mainstream CPU that forces them to compete with it, but otherwise I doubt it.

 

[pjbliverpool]

From a technical point of view, that would make a lot of sense for desktops, but not so much for laptops.

The business side is the problem. If Intel had to make chips with 2, 4, 8 cores, and scaled graphics EUs by as many levels, that would mean quite a lot of chips (up to 9, if every combination were implemented). I'm not sure Intel wants to bother with that; and I'm sure they don't want to eat into the Xeon market. They'll do it if AMD comes out with a really good 8-core mainstream CPU that forces them to compete with it, but otherwise I doubt it.

Yes I expect you're right. Then again, with Zen on the horizon and the rumours of Samsung purchasing AMD, we may be seeing a much more competitive AMD, and thus a much more exciting CPU landscape in the coming few years.

 

[fehu]

Samsung what?

 

[pjbliverpool]

Samsung what?

http://wccftech.com/amd-allegedly-merge-samsung/

 

[fehu]

Isn't wctech the new fudzilla?

 

[AlexV]

Yes I expect you're right. Then again, with Zen on the horizon and the rumours of Samsung purchasing AMD, we may be seeing a much more competitive AMD, and thus a much more exciting CPU landscape in the coming few years.

Samsung has been purchasing AMD for at least half a decade now. Before that it was Arabian princes from ATIC. Seems like this is either a complicated transaction or the expectation of AMD getting a sugar daddy is a bit too optimistic.

 

[3dilettante]

Was reading an article the other day talking about how they bought back a bunch of the old big AMD names for this.

I am not going to bet against those hires as being a sign of reconstituting a refocused development division, but it takes more than a few headliners at the top to make a platform and architecture. It's a wait and see situation at this point. The 4-5 year time window if AMD did an about-face after Bulldozer is not yet over, but a lot of the direction would be set down by this points.
The return of names like Keller might have made AMD fans oddly effusive as to his godlike power, but that was the latter half of 2012.

That's just the CPU, and getting that part back on track is simply not enough when processor design these days is an all-fronts effort in terms of system design, protocols, platform features, software/firmware collaboration, and manufacturing coordination. AMD has not kept up very well, and has spun of a lot of experienced staff in fields where it was theoretically better than a number of mobile-focused teams. There's the hope that the trailing off of AMD's CPU advances means more has been concentrated on a clean sheet that discards the increasingly chaotic underpinnings of their APU infrastructure, but latest rumors about AMD's R&D budget shrinking do not look promising.

The next question that should be answered soon is how many of Intel's extensions Zen picks up. If things like HLE and transactional memory show up, it's possible that AMD has some ambition in its design efforts.

If they go for high-end servers, they are crazy. They are road-kill in that space. Does anyone seriously think they have the resources to turn that around? Especially whilst at the same time tackling all the other markets? Smacks of wishful thinking to me.

AMD's greater emphasis has so far been the single-SOC density server play, whose standards are not as stringent and where AMD could afford to coast on the work it did for more demanding markets--if this were several years ago anyway. AMD's appears to have flubbed the SeaMicro approach as well, and it's waited long enough for Intel to put out Xeon D.
AMD has further reduced its staffing for things like high-speed IO, which CPU sockets talking to each other would like.

 

[itsmydamnation]

None of the things you listed are what took revenue away and none of them are what will get it back. Good straight line speed, look at what most servers are 2P esxi/hyper v hosts running a million VM's that aren't doing much. AMD's existing server infrastructure if perfectly fine for that. What they need is a solid core and cache design.

They dont need to be all things to all people, they just need a proper solid foundation, which is what the bulldozer core lost them. Some solid server revenue will get them looking a lot better quite quickly. They can be ambitious without chasing the latest buzzwords that wont matter for most software servers actually run.

 

[3dilettante]

None of the things you listed are what took revenue away and none of them are what will get it back. Good straight line speed, look at what most servers are 2P esxi/hyper v hosts running a million VM's that aren't doing much. AMD's existing server infrastructure if perfectly fine for that. What they need is a solid core and cache design.

AMD's server offerings have been stuck on old PCIe connectivity and old HT. The uncore that ties all those caches together is very old, which would constrain the design even if the cores and caches were replaced. AMD's server chips are using years old power management, which applies to the uncore, memory, and IO as well. The advanced management has elsewhere would need a new socket.

They dont need to be all things to all people, they just need a proper solid foundation, which is what the bulldozer core lost them. Some solid server revenue will get them looking a lot better quite quickly. They can be ambitious without chasing the latest buzzwords that wont matter for most software servers actually run.

Advanced methods of memory speculation would point to an overhaul of the subsystem. HLE and transactional memory require more in support than a new encoding.
It's a sign if they turn out to be supported that AMD has done something interesting.

 

[Kaotik]

http://www.fudzilla.com/news/processors/37494-amd-x86-16-core-zen-apu-detailed

Don't know if the slide is genuine or Fudzilla's make-belief, but it claims there will be APU with 16 Zen-cores (32 threads), "Greenland" graphics with 1/2 DP-rate, HBM memory + 4 channels of DDR4

 

[3dilettante]

There's nothing that screams "wrong" outright. It's a decent enough extrapolation from things that are ongoing, although a Greenland time-frame device with those bandwidth numbers might not be that great, unless Greenland closer to being a Fiji variant rather than of the generation after next.

There are other things that just seem sloppy, like having an APU with "Zen" cores and "Greenland" stream processor (sic), or "1Gbit" (assuming Ethernet would be in that box?).

 

[Raqia]

If the slide's correct, it's interesting that they're still opting for separate memory controllers for the CPU and GPU. Perhaps there's power savings to be had for each to be separate.

 

[Kaotik]

If the slide's correct, it's interesting that they're still opting for separate memory controllers for the CPU and GPU. Perhaps there's power savings to be had for each to be separate.

Or they both share the HBM and DDR4

 

[RedVi]

For a server CPU/APU, there is no way around including a DDR4 controller since abundances of RAM are necessary. The high end desktop chips will probably be the same but with less CPU cores (if they too, are APU's and not CPU only like Intel's high end). However, for mainstream APU's of the 4-6 core variety, 16GB HBM might be all that is needed even for 2017. If that is the plan then surely all the APU's would be designed with the CPU capable to sharing the HBM with the GPU. Hell, it could even act as a sort of L4 cache for the CPU and a way to quickly transfer between CPU and GPU.

 

[pTmdfx]

Hell, it could even act as a sort of L4 cache for the CPU and a way to quickly transfer between CPU and GPU.

Or just write it to your cache hierarchy, and let the GPU read it out from there (cache coherency, yah!). Even if you have a capacity miss, at worst case it is just going to the system memory, which is 83 GB/s for DDR4-2667 in this alleged APU. The nice thing is your HBM stacks are free from the overheads of working as a cache, and the GPU can enjoy the full bandwidth for any memory buffers that needn't be visible to the system.

IMO there is still a sea of better options than commodity DRAM as a cache, frankly. Let's say HMM in Linux.

 

[lanek]

For a server CPU/APU, there is no way around including a DDR4 controller since abundances of RAM are necessary. The high end desktop chips will probably be the same but with less CPU cores (if they too, are APU's and not CPU only like Intel's high end). However, for mainstream APU's of the 4-6 core variety, 16GB HBM might be all that is needed even for 2017. If that is the plan then surely all the APU's would be designed with the CPU capable to sharing the HBM with the GPU. Hell, it could even act as a sort of L4 cache for the CPU and a way to quickly transfer between CPU and GPU.

With HSA, both system and gpu memory can be accessed by the cpu and the gpu, it make the implementation of a HBM+DDR4 memory stack even more interessant.

 

[Raqia]

Good points. A complex memory hierarchy like the Xeon Phi's sounds like a lot of engineering complexity and validation that AMD probably can't afford right now. I'm going to guess that they can shut off each depending on the desired configuration or most economical memory technology. The DDR4 controller will be fused off for consumer class products and just use HBMs which just solder to a small profile package and simplifies motherboard design. That will give excellent performance with simpler manufacturing. The servers class products will probably have sockets and DIMM slots and use the DDR4 controller exclusively.

 

[Grall]

The servers class products will probably have sockets and DIMM slots and use the DDR4 controller exclusively.

Why on earth would the server chip of all NOT use HBM memory? That's where you need the most oomph of all.

 

[pTmdfx]

The servers class products will probably have sockets and DIMM slots and use the DDR4 controller exclusively.

And by that you get a crippled GPU, unless you got an ideal workload which loves huge data sets but isn't bandwidth hungry (Ehm... but your GPU is supposed to be a data parallel monster!).

On the other hand, AMD would not be able to sell this thing to anywhere it can make profits. Let's say... workstations and gaming PCs? Frankly, I don't think they would go HBM exclusive after all. They can always sell APUs with minimum viable size of HBM and still requires external memory DIMMs for them.

Would that be a "complex memory hierarchy"? Unlikely, or how would your discrete graphics work today, anyway? Xeon Phi has that hardware-based caching thing and there is where the complexity lies. But your today's GPUs are already having its own pool alongside your system memory, and more importantly, it works for years, is proven and is in use. Just that it is not convienent to use.

 

[pTmdfx]

Ugh, timed out. Please let me finish it.

Just that it is not convenient to use.

...in the past. Upcoming programming models give lots of control to developers' hands. On top of that the GPU (esp. the integrated one) also gains (or will gain) new capacities like cache coherent access to pageable system memory, which may free the GPU local memory for a better use. Like read from

P.S. Not sure if the KNL cache mode is really hardware based, but I assume it is...